Semiconductor Principal Design Engineer, Non‑Volatile Engineering Group - Tokyo, Japan
Originally posted 21 July 2026 by the employer.
About the role
This role involves owning and evolving timing-critical circuitry between the NAND array and page buffer, with a focus on delivering robust, scalable datapath solutions.
What you'll do
- Own internal NAND datapath circuits, including array redundancy circuits, wave pipeline / pulse based datapath architecture, and data line sensing circuits.
- Define and analyze clock/data timing schemes for long interconnects and large-array topologies; lead timing adjustment and skew management strategy.
- Drive layout-aware circuit design with attention to matching/symmetry, shielding/guarding, parasitic-aware sizing, RC-driven timing closure, array pitch constraints, blockages, and repeatable layout templates.
- Perform SPICE/Fast-SPICE simulations across PVT, aging, and variability via Monte Carlo.
- Lead design reviews, communicate tradeoffs (PPA, margin, schedule, risk), and propose mitigation plans.
- Communicate with project integration and other functional teams on specifications of major block interfaces.
What you'll need
- BS or MS in Electrical Engineering with 8+ years of relevant experience.
- Experience in physical design flows and optimization.
- Proven ownership of blocks from concept -> design -> layout -> signoff -> silicon correlation.
- Deep expertise in CMOS analog/mixed-signal circuit design and device physics fundamentals.
- High-speed datapath timing analysis, including nontraditional timing such as wave-pipelined/pulse-based.
- Expertise in layout parasitics and physical implementation impact on circuit behavior.
- Strong simulation and debug skills (SPICE/Fast-SPICE, corner/MC analysis, failure-mode thinking).
- Experience with managing complex design projects, effectively communicating progress and outcomes.
Nice to have
- Direct experience in NAND datapath and/or DRAM datapath design.
- Wave-pipelining, self-timed, or pulse-latched pipeline design techniques.
- Redundancy/repair architecture experience in dense arrays.
- Experience on DRAM interface (e.g. DDR4/5, LPDDR5/6, HBM3/3E/4) as well as other industry standard interfaces.
- Comprehensive understanding on CMOS device and device reliability.
Skills: NAND datapath circuits, wave pipeline / pulse based datapath architecture, data line sensing circuits, clock/data timing schemes, layout-aware circuit design, SPICE/Fast-SPICE simulations
This role has been open 152 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: NAND datapath circuits, wave pipeline / pulse based datapath architecture, data line sensing circuits, clock/data timing schemes, layout-aware circuit design, SPICE/Fast-SPICE simulations
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.