Semiconductor Layout & Tape-Out Engineer - Kodaira, Japan
Originally posted 6 October 2026 by the employer.
This role focuses on end-to-end tape-out execution for Gallium Nitride (GaN) technologies.
About the role
This role is responsible for end-to-end tape-out execution for Gallium Nitride (GaN) technologies. It supports multiple concurrent tape-out flows, ensuring accurate, high-quality mask data delivery.
What you'll do
- Perform and support PCM (Process Control Monitor) layout development and verification.
- Design and maintain alignment mark layouts in compliance with lithography and process requirements.
- Run Design Rule Checks (DRC) and mask data validation.
- Execute mask data generation workflows in accordance with foundry requirements.
- Perform mask data verification and signoff, ensuring format accuracy and rule compliance.
- Manage tape-out (TO) submissions and mask ordering processes.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Materials Science, Physics, or a related field.
- Familiarity with reticle design and mask data preparation flows.
- Basic understanding of mask data formats (e.g., MEBES/JobDeck).
- Proficiency in layout and verification tools such as Cadence and Calibre.
- Experience working in a Unix/Linux environment.
- Japanese language proficiency and good communication skills in English.
Nice to have
- Experience in foundry tape-out processes.
- Experience working in cross-functional, global engineering environments.
- LEDIT experience.
Skills: PCM layout, mask data preparation, tape-out, DRC, Cadence and Calibre
This role has been open 0 days — well below the 84-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
692
|
Median days open
84 d
|
Median salary
$193k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (692 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 692 |
| Open roles in the wider Physical Implementation family | 39 | 1430 · 108 employers |
| Median days open | 84 d | 84 d (same as this employer) |
| Median salary (USD postings) | — | $193k |
Skills observed across this category: PCM layout, mask data preparation, tape-out, DRC, Cadence and Calibre
Who's hiring in this category
- Cadence Design Systems · 165 open roles · median 167 d
- Synopsys · 52 open roles · median 35 d
- NVIDIA · 41 open roles · median 73 d
- Micron Technology · 40 open roles · median 114 d
- Qualcomm · 37 open roles · median 74 d
- GlobalFoundries · 28 open roles · median 51 d
How we counted: 692 open EDA/CAD Engineering (EDA Tools) roles from 76 employers tracked in the SemiconductorJobs index, counted 6 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.