Security IP Verification Engineer - Austin, Texas, United States
$161,500 - $218,500 USD yearly
Originally posted 6 August 2026 by the employer.
About the role
This role involves the design specification, test planning, testbench development, verification, and productization of Security IP for pioneering SoC designs, specifically focusing on Hardware Security IP and embedded processor systems.
What you'll do
- Define and realize Hardware Security IP and subsystems.
- Develop test plans, testbenches, verification models, and test strategies.
- Partner with the design team for functional sign-off and comprehensive coverage.
- Craft test plans and develop UVM, SystemVerilog/Verilog, and C testbenches and tests.
- Debug test failures and issues.
- Contribute to the development and enhancement of design and verification methodologies.
What you'll need
- 5+ years of experience in design or verification of sophisticated IP, embedded compute subsystems, or SoCs.
- Solid understanding of digital hardware Verilog HDL and Verification strategies including SystemVerilog UVM, C, Formal, and Hardware/Firmware co-verification.
- Verification experience in Security Hardware, Embedded Processor Systems, Applied Cryptography, Secure Boot, and Key Management.
- Experience in complex digital IP architecture and development including multi-clock domain designs, AXI/AHB protocols, multi-power domains, and reset architectures.
- Experience with Perl, Python, Tcl, or other scripting languages.
- Experience verifying IP or SoC projects or systems including embedded microprocessors, with a preference for firmware/hardware co-verification or formal verification.
- Low-level programming experience including C and Assembler, and experience with firmware debug and tarmac logging.
Nice to have
- Experience with Arm-based designs and/or ARM System Architectures.
- Clock domain crossing verification.
- Power aware verification.
Skills: Hardware Security IP, UVM, SystemVerilog, testbenches, formal verification, embedded processor
This role has been open 72 days — slightly above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1202
|
Median days open
65 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1202 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 1202 |
| Open roles in the wider Digital Design & Verification family | 104 | 3201 · 115 employers |
| Median days open | 103 d | 65 d (+38 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: Hardware Security IP, UVM, SystemVerilog, testbenches, formal verification, embedded processor
Who's hiring in this category
- Qualcomm · 110 open roles · median 39 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 84 open roles · median 59 d
- Synopsys · 64 open roles · median 33 d
- SiFive · 55 open roles · median 75 d
- Cadence Design Systems · 50 open roles · median 117 d
How we counted: 1202 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.