$149,100 - $238,200 USD yearly
Originally posted 5 November 2026 by the employer.
About the role
As an RTL Engineer, you will design, implement, and verify high-performance digital logic targeting advanced FPGA and programmable logic platforms for Physical AI workloads.
What you'll do
- Design and develop synthesizable Verilog and SystemVerilog RTL for FPGA and programmable hardware solutions supporting Physical AI applications.
- Create microarchitecture specifications, participate in architecture reviews, and optimize designs for performance, area, power, and scalability.
- Collaborate with design verification teams to define verification strategies and close functional coverage.
- Support FPGA implementation activities including synthesis, timing closure, static timing analysis, and performance analysis.
- Work with firmware and software teams to enable hardware-software integration, system bring-up, and debug RTL across simulation, emulation, and silicon.
What you'll need
- Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- 3+ years of experience in RTL design and digital logic development.
- Expertise in Verilog and/or SystemVerilog.
- Understanding of computer architecture, digital design fundamentals, and ASIC/FPGA design methodologies.
- Experience with simulation, debugging, and verification tools.
- Experience developing high-performance datapath, control logic, or accelerator architectures.
- Familiarity with synthesis, static timing analysis, and FPGA implementation flows.
Nice to have
- Master's or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline.
- Experience designing AI, machine learning, vision-processing, signal-processing, networking, or robotics accelerators.
- Knowledge of FPGA architectures and adaptive computing platforms.
- Experience with industry-standard EDA tools such as Synopsys, Siemens EDA, or Cadence design environments.
- Understanding of high-bandwidth memory systems, NoC architectures, PCIe, Ethernet, CXL, or coherent interconnects.
- Experience with hardware/software co-design.
- Familiarity with Python, C/C++, or scripting languages used for design automation and validation.
- Experience developing solutions for robotics, industrial automation, autonomous systems, or edge AI applications.
More semiconductor jobs: Altera jobs · RTL design jobs · San Jose jobs
This role has been open 0 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1086
|
Median days open
61 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Altera | All employers we track in this specialty (1086 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 1086 |
| Open roles in the wider Digital Design & Verification family | 27 | 3495 · 120 employers |
| Median days open | 22 d | 61 d (−39 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Who's hiring in this category
- Qualcomm · 142 open roles · median 71 d
- Synopsys · 90 open roles · median 48 d
- AMD · 78 open roles · median 47 d
- NXP Semiconductors · 45 open roles · median 104 d
- NVIDIA · 44 open roles · median 61 d
- Analog Devices · 41 open roles · median 51 d
How we counted: 1086 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.