RTL Engineer - Mountain View, CA, United States
$215,000 USD yearly
Originally posted 1 July 2026 by the employer.
Design RTL for AI accelerators.
About the role
Design the RTL that defines the AI accelerator. This includes architecting and implementing digital blocks like the compute datapath, memory subsystem, on-chip interconnect, and control logic from microarchitecture specification through synthesis-ready, timing-clean RTL.
What you'll do
- Own RTL design of digital blocks/subsystems for the accelerator, including microarchitecture definition, SystemVerilog implementation, and integration. - Translate architectural specifications into efficient, synthesizable RTL that meets power/performance/area (PPA) targets. - Drive microarchitecture trade-offs, such as pipelining, datapath vs. control, and clock/power gating for high-performance, low-power design. - Partner with Design Verification (DV) on verification, Physical Design (PD) on synthesis/timing/floorplan closure, and Design For Test (DFT) on testability. - Own block-level quality including synthesis, timing/constraints (SDC, STA), lint, and CDC signoff. - Contribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-up.
What you'll need
- Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL. - 5+ years designing complex digital blocks/SoCs taken to silicon. - Solid microarchitecture skills including pipelining, datapath/control, FIFOs, arbitration, memory subsystems, and on-chip interconnect/NoC. - Synthesis & timing awareness: writing synthesizable RTL, SDC constraints, STA, clock/power gating, and CDC, lint. - Demonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeout. - Scripting (Python/Tcl) for design automation.
Nice to have
- AI/ML accelerator or high-performance compute-datapath design. - Low-power techniques (UPF). - High-speed interfaces (HBM, PCIe, SerDes). - Advanced nodes (7nm or better). - RISC-V/CPU design. - FPGA prototyping.
This role has been open 34 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | DensityAI | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1021 |
| Open roles in the wider Digital Design & Verification family | 5 | 3191 · 115 employers |
| Median days open | 34 d | 61 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 134 open roles · median 64 d
- Synopsys · 86 open roles · median 29 d
- AMD · 72 open roles · median 35 d
- Analog Devices · 49 open roles · median 47 d
- NVIDIA · 46 open roles · median 63 d
- NXP Semiconductors · 41 open roles · median 84 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.