RTL Engineer Memory Subsystem - Santa Clara, CA, United States

Originally posted 16 September 2026 by the employer.

This role focuses on the high-speed, low-power memory subsystem that feeds Velaura's Physical AI SoC.

About the role

This role involves building Velaura's Physical AI SoC, focusing on the high-speed, low-power memory subsystem. You will own significant portions of the memory subsystem design, contributing to microarchitectural decisions and delivering high-performance, power-efficient hardware.

What you'll do

• Design, implement, and optimize RTL for the memory subsystem, including memory controllers, fabric interfaces, and logic integrating with external memory PHYs.
• Own memory controller and PHY integration, including DFI, initialization and training flows, calibration, and bring-up hooks.
• Drive high-speed, low-power design of the memory path, including timing closure, power-state management (self-refresh, power-down), clock and power gating, and DVFS interactions.
• Work with software teams to define hardware interfaces, memory maps, execution flows, and performance-critical interactions such as scheduling, prefetching, and quality of service.
• Analyze bandwidth, latency, and utilization bottlenecks in the memory path and propose architectural and implementation improvements.
• Optimize designs for performance, power, area, scalability, and reliability, including RAS features such as ECC and error reporting.

What you'll need

• Experience designing RTL for complex digital systems, with hands-on ownership of memory subsystem blocks.
• Demonstrated experience integrating a memory controller with a memory PHY, including DFI, initialization and training sequences, and bring-up.
• Strong understanding of high-speed, low-power memory technologies such as LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, DDR, and HBM, including protocol, timing, and power-state behavior.
• Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
• Expert-level Verilog and SystemVerilog skills and experience with modern RTL design methodologies, including lint, clock-domain crossing analysis, synthesis-aware coding, and low-power intent.
• Familiarity with performance, power, and area tradeoffs in the memory path.

Nice to have

• Familiarity with standard interconnect protocols such as AXI, CHI, and ACE on the controller's system-side interface, including quality-of-service mechanisms.
• Experience with memory controller and PHY bring-up on silicon, including training and calibration debug and margining.
• Knowledge of reliability, availability, and serviceability in the memory path, including inline and side-band ECC, scrubbing, poisoning, and error reporting.
• Experience with low-power design techniques and power management architectures across memory and clock and power domains.
• Experience developing a memory controller from the ground up, including command scheduling and arbitration, bank and rank management, refresh management, and reordering.
• Knowledge of functional safety standards such as ISO 26262 and ASIL as they apply to memory-path design.
• Experience with AI, machine learning, or edge AI hardware, especially the memory access patterns of tensor workloads.
• Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.