RTL Design Engineer, Hardware - Palo Alto, CA, United States
$200,000 - $420,000 USD yearly
Originally posted 15 May 2026 by the employer.
About the role
This role architects and implements high-performance custom silicon, defining the architecture, micro-architecture, and implementation of AI accelerator and related SoC components on advanced foundry nodes. You will take ownership of chip subsystems and drive both functionality and PPA while collaborating with compiler, performance modeling, verification, and physical design teams.
What you'll do
- Create high-level architectural specifications and detailed micro-architectural designs for AI hardware subsystems. - Design and implement complex logic using System Verilog, focusing on pipelines, throughput versus latency tradeoffs, and power-efficient data paths. - Collaborate with the backend team on synthesis, floorplanning, and power analysis. - Drive and analyze static timing analysis (STA) to resolve timing violations and ensure the design meets target frequencies. - Collaborate with compiler, performance modeling, and software teams to identify bottlenecks across micro-architecture, architecture, ISA, kernels, and end applications.
What you'll need
- Bachelor’s degree in Electrical Engineering or Computer Engineering, and 5+ years of practical industry experience working with advanced process nodes (7nm or below). - Hands-on proficiency with RTL, synthesis, physical design, and timing tools, including System Verilog, VCS/Verdi, Fusion Compiler, and PrimeTime. - Computer architecture knowledge of at least one style of chip, including SoCs, CPUs, GPUs, or AI accelerators. - Track record of functional and performant silicon delivery, including experience in ECOs and reliable silicon at scale.
Nice to have
- Hands-on experience in post-Silicon bug fixing, firmware patching, and GPIO/I2C/SPI/UART low-level debugging. - Proficiency with C/C++/Python and ISA assembly to understand and debug performance models and kernels. - Experience with high-speed IO devices such as PCIe, UCIe, or HBM/DDR memory controllers. - Knowledge of NoC level communications, such as AXI, CHI, or credit or valid/ready protocols.
This role has been open 130 days — well above the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1078
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | River | All employers we track in this specialty (1078 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1078 |
| Open roles in the wider Digital Design & Verification family | 3 | 3322 · 115 employers |
| Median days open | 130 d | 63 d (+67 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 157 open roles · median 59 d
- Synopsys · 88 open roles · median 36 d
- AMD · 76 open roles · median 41 d
- Analog Devices · 49 open roles · median 52 d
- NXP Semiconductors · 42 open roles · median 91 d
- NVIDIA · 40 open roles · median 63 d
How we counted: 1078 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.