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Synopsys

R&D Engineering, Sr Engineer

Synopsys img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Noida, India 21 days ago
Digital Design & SoC Architecture

Originally posted 14 September 2026 by the employer. Relisted by the employer on 30 September 2026.

About the role

This role involves the design and optimization of SRAM bitcells and peripheral circuits for power, performance, area, and yield. The focus includes memory solutions that power AI, mobile, automotive, and networking silicon.

What you'll do

  • Design and optimize SRAM bitcells and peripheral circuits including sense amplifiers, write drivers, precharge circuits, and row/column decoders.
  • Run transistor-level simulations using SPICE-class tools to validate circuit behavior.
  • Perform Monte Carlo and variability analysis to ensure robust operation.
  • Contribute to SRAM compiler development and automation flows using scripting languages like Python, Perl, or Tcl.
  • Debug circuit failures, analyze noise margins, and implement read/write assist techniques.
  • Document design decisions, simulation results, and circuit methodologies.

What you'll need

  • B.Tech or M.Tech in Electrical Engineering, Electronics Engineering, VLSI Design, or Microelectronics.
  • 0-2 years of experience in circuit design, VLSI engineering, or memory design (internships, projects, and relevant coursework included).
  • Strong foundation in CMOS device physics, transistor operation, and semiconductor process technology.
  • Understanding of SRAM architecture, bitcell design, and memory circuit fundamentals.

Nice to have

  • Familiarity with scripting languages like Python, Perl, or Tcl.
  • Experience with SRAM compiler development.
  • Experience with advanced node design challenges.
  • Published work in memory design.

Skills: SRAM bitcells, sense amplifiers, write drivers, memory compiler, SPICE, circuit design

Market context

This role has been open 20 days — well below the 69-day median for Memory Design roles.

Memory Design · Memory Design

Open roles in category
287
Median days open
69 d
Median salary
$205k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Synopsys compares in Memory Design hiring
Metric Synopsys All employers we track in this specialty (287 roles · 29 employers)
Open roles in this specialty 27 287
Median days open 49 d 69 d (−20 d vs this employer)
Median salary (USD postings) — $205k

Skills observed across this category: SRAM bitcells, sense amplifiers, write drivers, memory compiler, SPICE, circuit design

Who's hiring in this category

  • Micron Technology · 151 open roles · median 86 d
  • Synopsys (this employer) · 27 open roles · median 49 d
  • SanDisk · 17 open roles · median 32 d
  • Broadcom · 16 open roles · median 50 d
  • Qualcomm · 12 open roles · median 149 d
  • NVIDIA · 7 open roles · median 59 d

How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.

Synopsys

Synopsys

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img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Noida, India
On-site
21 days ago

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