R&D Engineering Scientist
Originally posted 25 October 2026 by the employer.
About the role
Synopsys is seeking an R&D Engineering Scientist to own high-speed PHY architecture, including protocols, data rates, BER, and PPA targets. This role focuses on defining 112 Gb/s and 224 Gb/s PAM4 PHY architectures across analog, digital, package, and channel domains.
What you'll do
- Define data-path and clocking architectures, including modulation, equalization, FEC placement, ADC-DSP, PLL, and CDR.
- Lead calibration and adaptation strategies across process, voltage, temperature, and channel conditions.
- Allocate power, area, performance, and latency across analog, digital, and package components while closing the end-to-end link budget.
- Develop block specifications for engineering implementation and verification.
- Define architecture sign-off, modeling, observability, and silicon bring-up requirements, including loopback, PRBS, eye scan, and calibration access.
- Align standards, signal and power integrity, package, and program teams on guaranteed IP performance.
What you'll need
- Strong architectural knowledge of 112 Gb/s and 224 Gb/s PAM4 serial links.
- Expertise in link budgeting, insertion and return loss, crosstalk, jitter, BER, channel operating margin, and FEC coding gain.
- Deep knowledge of CTLE, FFE, DFE, ADC-DSP, PLL, CDR, adaptation, and calibration.
- Experience with channel and behavioral modeling, process-corner analysis, and analog, digital, and package PPA tradeoffs.
- Silicon bring-up and debug experience using PRBS, loopback, eye scan, and calibration capabilities.
- Demonstrated ability to write clear technical specifications and explain architecture decisions to technical, program, and customer audiences.
Skills: PAM4, 112 Gb/s, 224 Gb/s, PHY Architecture, CDR, CTLE
More semiconductor jobs: Synopsys jobs · Signal integrity jobs · Sunnyvale jobs
This role has been open 0 days — well below the 72-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
246
|
Median days open
72 d
|
Category median salary (all employers)
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (246 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 35 | 246 |
| Open roles in the wider Analog & Mixed-Signal family | 57 | 1520 · 106 employers |
| Median days open | 36 d | 72 d (−36 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: PAM4, 112 Gb/s, 224 Gb/s, PHY Architecture, CDR, CTLE
Who's hiring in this category
- Synopsys (this employer) · 34 open roles · median 40 d
- AMD · 26 open roles · median 46 d
- Cadence Design Systems · 21 open roles · median 144 d
- Qualcomm · 19 open roles · median 73 d
- Micron Technology · 13 open roles · median 45 d
- Apple · 9 open roles · median 28 d
How we counted: 246 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.