$74,000 - $118,800 USD yearly
Originally posted 6 November 2026 by the employer.
About the role
Broadcom is seeking an R&D Engineer, IC Design to write assertions and design verification tests for chip-level and block-level models.
What you'll do
- Write and maintain assertions and DV tests for chip-level and block-level models.
- Gather design data directly from circuit designers.
- Create netlists and use AI to create models, including real-number models.
- Write tests to verify the functional accuracy of the models.
- Write code in Python to automate design verification tasks.
What you'll need
- Bachelor's degree in Computer Science, Electrical Engineering, or a related field.
- Minimum of 2 years of relevant experience.
- Working knowledge of Verilog/SystemVerilog.
- Working knowledge of the Linux operating system.
- Familiarity with Cadence Virtuoso.
- Proficiency with Python, Git, JIRA, Windows, and Google Office suites.
Nice to have
- Experience with real-number modeling.
- Experience with AI-assisted development tools.
Skills: SystemVerilog, assertions, real-number modeling, DV, Virtuoso
More semiconductor jobs: Broadcom jobs · Verification engineer jobs
This role has been open 0 days — well below the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1336
|
Median days open
57 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (1336 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 21 | 1336 |
| Open roles in the wider Digital Design & Verification family | 70 | 3493 · 120 employers |
| Median days open | 44 d | 57 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, assertions, real-number modeling, DV, Virtuoso
Who's hiring in this category
- Qualcomm · 116 open roles · median 50 d
- Apple · 111 open roles · median 9 d
- NVIDIA · 104 open roles · median 72 d
- AMD · 81 open roles · median 66 d
- Synopsys · 74 open roles · median 50 d
- SiFive · 57 open roles · median 64 d
How we counted: 1336 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.