$109,700 - $175,500 USD yearly
Originally posted 14 July 2026 by the employer. Relisted by the employer on 6 November 2026.
About the role
Broadcom is seeking a semiconductor professional with experience in predicting wafer-level yield and optimizing PPA from SoC telemetry and volume ATE production test data. The work focuses on designing and deploying ML, DL, and GenAI tools that translate silicon data into actionable yield and performance optimization strategies.
What you'll do
- Design, build, and deploy ML, DL, and GenAI models to predict and maximize wafer-level yield using large-scale SoC telemetry data.
- Organize, clean, and analyze large, multi-source sensor databases and provide input on future telemetry requirements.
- Interpret complex parametric data, on-chip sensor readouts, and circuit telemetry to isolate failure mechanisms and marginalities.
- Partner with foundry, product engineering, design-for-manufacturing (DFM), and DFT engineering teams to drive yield and PPA strategies.
- Develop, qualify, and productize experimental data workflows and collaborate with teams to release them to scalable production.
- Perform circuit analysis using SPICE modeling tools, Cadence Virtuoso, and Primetime STA tools.
What you'll need
- MS in Electrical Engineering, Computer Science, or a related field plus 6 years of experience, or Ph.D. plus 3 years of experience.
- Track record in the semiconductor industry specializing in silicon macro characterization and SoC telemetry analysis.
- Experience applying Machine Learning and Artificial Intelligence techniques (such as deep learning, anomaly detection, and multivariate regression) to physical hardware datasets.
- Hands-on experience with SPICE modeling tools, Cadence Virtuoso, and familiarity with Primetime STA tools.
- Programming skills in Python, R, or C++ and hands-on experience handling massive databases.
- Understanding of semiconductor manufacturing processes, wafer fabrication, DFM practices, and electronic design automation (EDA) tools.
Skills: precision analog blocks, ADCs, DACs, regulators, Cadence Virtuoso, SPICE simulators, silicon validation
More semiconductor jobs: Broadcom jobs · Mixed-signal design jobs
This role has been open 115 days — slightly above the 114-day median for Mixed-Signal Design roles.
Mixed-Signal Design · Mixed Signal
|
Open roles in category
162
|
Median days open
114 d
|
Category median salary (all employers)
$183k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (162 roles · 41 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 162 |
| Open roles in the wider Analog & Mixed-Signal family | 31 | 1549 · 114 employers |
| Median days open | 78 d | 114 d (−36 d vs this employer) |
| Median salary (USD postings) | — | $183k |
Skills observed across this category: precision analog blocks, ADCs, DACs, regulators, Cadence Virtuoso, SPICE simulators, silicon validation
Who's hiring in this category
- NVIDIA · 20 open roles · median 184 d
- Analog Devices · 14 open roles · median 136 d
- SiTime · 11 open roles · median 226 d
- Apple · 9 open roles · median 22 d
- Infineon Technologies · 9 open roles · median 113 d
- Microchip Technology · 8 open roles · median 225 d
How we counted: 162 open Mixed-Signal Design (Mixed Signal) roles from 41 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.