Design and validate DDR and high-bandwidth memory physical layer interfaces for machine learning accelerator chips.
About the role
This role involves designing and validating high-bandwidth memory and DDR memory physical layer interfaces for machine learning accelerator chips and system-on-chip architectures. The work spans 2.5D packaging design, memory subsystem integration, and post-silicon validation and characterization.
What you'll do
- Design and validate high-bandwidth memory and DDR memory physical layer interfaces for machine learning accelerator chips and system-on-chip architectures.
- Integrate third-party intellectual property blocks into complex system-on-chip designs and perform advanced 2.5D packaging design for memory subsystems.
- Perform post-silicon validation and characterization of memory subsystems including bring-up, debug, and performance optimization.
- Define and implement boot-up initialization sequences, reset flows, and training algorithms for memory controllers and physical layer circuits.
- Collaborate with physical design teams to define timing constraints and review clock distribution networks for memory interfaces.
- Perform advanced system-level debugging and root-cause analysis of complex functional and performance issues across bring-up, characterization, validation, and production phases.
What you'll need
- Experience designing and validating DDR and high-bandwidth memory physical layer interfaces.
- Background in integrating third-party intellectual property blocks into complex system-on-chip designs and 2.5D packaging design for memory subsystems.
- Hands-on experience with post-silicon validation, characterization, bring-up, and performance optimization of memory subsystems.
- Experience defining and implementing boot-up initialization sequences, reset flows, and training algorithms for memory controllers and physical layer circuits.
- Expertise collaborating on timing constraints and clock distribution networks with physical design teams.
Skills: HBM, DDR, PHY, SoC, post-silicon validation
More semiconductor jobs: Amazon jobs · Signal integrity jobs · Austin jobs
This role has been open 0 days — well below the 76-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
255
|
Median days open
76 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (255 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 255 |
| Open roles in the wider Analog & Mixed-Signal family | 7 | 1545 · 113 employers |
| Median days open | 26 d | 76 d (−50 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Skills observed across this category: HBM, DDR, PHY, SoC, post-silicon validation
Who's hiring in this category
- Synopsys · 35 open roles · median 38 d
- AMD · 24 open roles · median 46 d
- Cadence Design Systems · 21 open roles · median 150 d
- Qualcomm · 17 open roles · median 84 d
- NVIDIA · 16 open roles · median 211 d
- Micron Technology · 11 open roles · median 49 d
How we counted: 255 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 51 employers tracked in the SemiconductorJobs index, counted 6 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.