Principal Product Technical Leader — AEC/SCM - San Jose, California, United States
$160,000 - $200,000 USD yearly
Originally posted 4 August 2026 by the employer.
This role focuses on CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
About the role
This role involves architecting and delivering connectivity silicon for AI clusters, with a focus on PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.
What you'll do
- Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
- Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.
- Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality.
- Partner with architecture to translate specifications into implementation-ready microarchitecture.
- Collaborate with verification on testplans, coverage closure, and bug triage.
- Mentor junior engineers and contribute to design methodology, scripts, and best practices.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of digital design experience, including at least one full chip from spec to tapeout.
- Strong proficiency in Verilog/SystemVerilog, RTL coding, and synthesis flows.
- Hands-on experience with timing closure, CDC, lint, and low-power design techniques.
- Solid understanding of high-speed serial interfaces (PCIe, Ethernet, or similar) and SoC integration.
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering.
- Experience with PCIe Gen5/Gen6, CXL, UALink, UCIe, or Ethernet MAC/PCS designs.
- Familiarity with formal verification, emulation, or assertion-based methodologies.
- Background in advanced process nodes (7nm, 5nm, or below).
- Strong debug skills across pre-silicon and post-silicon environments.
Skills: RTL Design, Verilog/SystemVerilog, synthesis, timing closure, PCIe, CXL, Ethernet
This role has been open 58 days — below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
980
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (980 roles · 100 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 980 |
| Open roles in the wider Digital Design & Verification family | 62 | 3112 · 115 employers |
| Median days open | 21 d | 61 d (−40 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL Design, Verilog/SystemVerilog, synthesis, timing closure, PCIe, CXL
Who's hiring in this category
- Qualcomm · 147 open roles · median 55 d
- Synopsys · 67 open roles · median 24 d
- AMD · 62 open roles · median 43 d
- NXP Semiconductors · 51 open roles · median 70 d
- Analog Devices · 46 open roles · median 37 d
- NVIDIA · 46 open roles · median 55 d
How we counted: 980 open Digital/RTL Design (RTL Design) roles from 100 employers tracked in the SemiconductorJobs index, counted 1 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.