Product Engineer (3D IC, Heterogeneous Integration & Advanced Packaging) - San Jose, United States
$136,500 - $253,500 USD yearly
Originally posted 21 May 2026 by the employer. Relisted by the employer on 24 September 2026.
About the role
As Product Engineer, you are responsible for driving the definition, early deployment, and broader adoption of the Cadence Virtuoso Heterogeneous Integration technologies. You collaborate across teams to define requirements, validate solutions, and support physical implementation flows for 3D IC, heterogeneous integration, and advanced packaging.
What you'll do
- Drive, validate, and promote an end-to-end solution for system design implementation flows spanning 3D IC, heterogeneous integration, and advanced packaging. - Partner with semiconductor customers to understand system co-design challenges and translate them into clear Product Requirement Specifications (PRS) and technical use cases. - Collaborate cross-functionally with R&D, Product Management, Field teams, Technical Publications, and Product Validation to deliver customer-ready capabilities. - Create and deliver demonstration collateral, application workflows, and enablement materials to support customer and field adoption. - Troubleshoot design-flow issues, provide technical guidance and workarounds, and drive bug and enhancement prioritization. - Support product launches, customer engagements, industry events, and own deliverables from definition through customer deployment.
What you'll need
- BS in Electrical Engineering, Electronics, or a related technical field. - 10+ years of relevant experience, or equivalent demonstrated expertise. - Experience in semiconductor design, physical implementation, advanced packaging, or EDA product engineering. - Hands-on knowledge of the Cadence Virtuoso platform and associated custom IC design flows.
Nice to have
- Experience with software product definition, validation, or technical marketing activities. - Experience with co-design flows around 3D IC, heterogeneous integration, and silicon-package-board integration. - Knowledge of Cadence Allegro Package Designer Plus (APD+) and package implementation methodologies. - Knowledge of Cadence Virtuoso SKILL language or another interpreted language.
Skills: post-silicon bring-up, debug, Memory IP subsystems, DDR5/4/3, LPDDR5/4/3, HBM3/4, GDDR6/7, lab equipment
This role has been open 215 days — well above the 59-day median for Product Engineering roles.
Product Engineering · Memory Design
|
Open roles in category
95
|
Median days open
59 d
|
Median salary
$149k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (95 roles · 13 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 95 |
| Open roles in the wider Silicon Validation & Test family | 27 | 2235 · 112 employers |
| Median days open | 215 d | 59 d (+156 d vs this employer) |
| Median salary (USD postings) | — | $149k |
Skills observed across this category: post-silicon bring-up, debug, Memory IP subsystems, DDR5/4/3, LPDDR5/4/3, HBM3/4, GDDR6/7, lab equipment
Who's hiring in this category
- Micron Technology · 56 open roles · median 82 d
- SanDisk · 14 open roles · median 66 d
- KIOXIA America · 8 open roles · median 27 d
- Solidigm · 4 open roles · median 4 d
- Cadence Design Systems (this employer) · 3 open roles · median 215 d
- OmniVision · 2 open roles · median 167 d
How we counted: 95 open Product Engineering (Memory Design) roles from 13 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.