Product Development/DFX Lead - Neuromorphic Computing - United States
$141,910 - $269,100 USD yearly
Originally posted 1 September 2026 by the employer.
Architect and drive innovative test, debug, and reliability solutions for Intel's neuromorphic silicon program, focusing on Loihi's asynchronous circuits and advanced integration technologies.
About the role
This role is for a senior product development engineer to lead the DFT/DFX strategy for Intel's neuromorphic silicon program. You will architect and drive innovative test, debug, and reliability solutions for Loihi's asynchronous circuits and advanced integration technologies.
What you'll do
- Architect a complete DFT solution at the SoC level, compiling requirements of both synchronous and asynchronous designs.
- Lead flow-development for scan-insertion and compression at partition and SoC levels.
- Build a scalable framework spanning EDA tools, RTL and emulation models to generate test vectors and validate them pre-silicon.
- Collaborate with designers to drive DFT/DFD/DFM features to ensure manufacturing readiness to support HVM.
- Lead silicon power-on, enabling tester content, debugging failures and maintaining tools/flows.
What you'll need
- 6+ years of hands-on DFT experience from architecture to silicon bring-up.
- 6+ years of experience of architecting the entire DFT stack including scan insertion, compression and ATPG vector generation.
- 4+ years of direct ownership of IP and SoC-level scan constructs, including boundary scan (JTAG), TAP, BIST/MBIST.
- 1 year of experience in debugging post-silicon and driving circuit changes for testability and reliability improvements.
Nice to have
- Experience in custom ASICS or AI/ML accelerator design.
- Experience in post-silicon bin split, die-level cherry picking (DLCP) and fault grading.
- Strong System-Verilog/System-C/OOP background with pre-silicon verification experience.
- Experience in test time reduction techniques on automatic test equipment (ATE).
- Experience in asynchronous architectures and circuits.
- 1+ year of experience using AI tools for setting up tool flows, debugging and improving overall productivity.
Skills: DFT, scan insertion, ATPG, MBIST, post-silicon debug
This role has been open 46 days — well below the 58-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
242
|
Median days open
58 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (242 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 8 | 242 |
| Open roles in the wider Digital Design & Verification family | 87 | 3202 · 115 employers |
| Median days open | 79 d | 58 d (+21 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Skills observed across this category: DFT, scan insertion, ATPG, MBIST, post-silicon debug
Who's hiring in this category
- AMD · 39 open roles · median 44 d
- NVIDIA · 23 open roles · median 36 d
- Qualcomm · 23 open roles · median 101 d
- NXP Semiconductors · 18 open roles · median 66 d
- Synopsys · 14 open roles · median 25 d
- Micron Technology · 10 open roles · median 65 d
How we counted: 242 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.