Product and Test Engineer - Manchester, NH, United States
Verification, Validation & Test
Originally posted 14 September 2026 by the employer — open 2 days.
About the role
This role involves developing, debugging, and sustaining production test solutions for isolated gate drivers within the High Voltage Power (HVP) business unit.
What you'll do
- Develop, debug, and optimize test programs on mixed-signal Automated Test Equipment (ATE) platforms (e.g., Teradyne ETS-364/ETS-88, LTX-Credence, or similar mixed-signal testers).
- Create test methodologies for wafer-level sorting (probe cards, Scribe Line Monitors) and final packaged testing (DIB/Load boards, high-speed sockets).
- Implement DFT methodologies including Short Voltage Elevation (SHOVE) stress testing, Gate Stress, and IDDQ/quiescent current screening.
- Design, verify, and document Device Interface Boards (DIB), load boards, and handler interface hardware, ensuring high voltage safety protocols.
- Execute characterization plans over voltage and temperature corners (-40°C to 125°C/150°C) and analyze test data using statistical process control (SPC) tools, DPAT, and SBL.
- Participate in DFT reviews with Analog/Digital Design Leads to define test modes, trim algorithms, and verify register/EEPROM configurations.
What you'll need
- Bachelor’s degree in Electrical Engineering, Electronic Engineering, or a related discipline.
- 2–6 years of experience in semiconductor Product and/or Test Engineering with high-voltage, analog mixed-signal, or power management ICs.
- Proficiency in writing and debugging ATE test code (C/C++ or specialized tester languages).
- Solid understanding of analog circuit fundamentals (operational amplifiers, LDOs, DACs, ADCs, gate driver stages).
- Familiarity with high-voltage test constraints, high CMTI environments, and galvanic isolation parameters.
- Experience with PCB design software (Altium, PCB Cadence or similar) for load board schematic/layout review.
- Knowledge of statistical analysis tools (such as Galaxy or similar) for yield and data log analysis.
Market context
This role has been open 2 days — well below the 27-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
341
|
Median days open
27 d
|
Median salary
$153k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Allegro MicroSystems | All employers we track in this specialty (341 roles · 66 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 341 |
| Open roles in the wider Silicon Validation & Test family | 11 | 1987 · 109 employers |
| Median days open | 5 d | 27 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $153k |
Who's hiring in this category
- Infineon Technologies · 32 open roles · median 26 d
- Renesas Electronics · 32 open roles · median 29 d
- Qualcomm · 23 open roles · median 19 d
- Micron Technology · 22 open roles · median 17 d
- AMD · 18 open roles · median 25 d
- NVIDIA · 16 open roles · median 22 d
How we counted: 341 open Silicon Test Engineering (DFT Test) roles from 66 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.