Process Engineer – Die to Wafer Hybrid Bonding - Santa Clara, CA, United States
$147,000 - $202,500 USD yearly
Originally posted 27 July 2026 by the employer.
About the role
Process Engineers design and optimize manufacturing processes for display and semiconductor manufacturing technologies while collecting data, performing hardware characterization, and troubleshooting engineering issues. In this role within the Photonics Platforms Business Group, you will focus on die to wafer (D2W) hybrid bonding process development, pathfinding, technology de-risking, and advanced packaging integration exploration.
What you'll do
- Develop die to wafer hybrid bonding processes, covering surface preparation and plasma activation, high accuracy die placement and alignment, and post-bond characterization and process evaluation. - Integrate D2W bonding with adjacent process modules, including dicing and die preparation, die thinning, and inter-die gap fill and planarization. - Design and execute DOE-driven experiments to identify process limits, sensitivities, and trade-offs. - Own process optimization, perform failure analysis and characterization, and drive continuous engineering improvement. - Measure film properties, generate technical documentation, and collaborate with vendors, suppliers, and cross-functional research teams.
What you'll need
- Ph.D. or M.S. in Materials Science, Electrical Engineering, Applied Physics, or a related STEM discipline. - In-depth knowledge and hands-on experience in one or more of the following: die to wafer or wafer to wafer hybrid bonding; thin die handling and alignment critical processes; Micro-LED or CPO experience; heterogeneous integration such as III-V to Si or novel materials to Si; 2.5D/3D integration; or direct process engineer experience on mainstream semiconductor equipment (plasma, wet clean, overlay/alignment). - Strong understanding of bond interface physics, alignment and overlay fundamentals, and the mechanical behavior of thin and fragile dies. - Proficiency in statistical analysis and process control, including DOE, SPC, and JMP.
Skills: hybrid bonding, die-to-wafer, film properties, hardware characterization, process optimization
This role has been open 180 days — well above the 72-day median for Process Engineering roles.
Process Engineering · Semiconductor Process
|
Open roles in category
1052
|
Median days open
72 d
|
Median salary
$137k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Applied Materials | All employers we track in this specialty (1052 roles · 56 employers) |
|---|---|---|
| Open roles in this specialty | 79 | 1052 |
| Open roles in the wider Process, Fab & Equipment family | 1124 | 10037 · 107 employers |
| Median days open | 72 d | 72 d (same as this employer) |
| Median salary (USD postings) | — | $137k |
Skills observed across this category: hybrid bonding, die-to-wafer, film properties, hardware characterization, process optimization
Who's hiring in this category
- Micron Technology · 334 open roles · median 132 d
- GlobalFoundries · 88 open roles · median 89 d
- Applied Materials (this employer) · 79 open roles · median 72 d
- Texas Instruments · 57 open roles · median 55 d
- STMicroelectronics · 50 open roles · median 48 d
- Entegris · 43 open roles · median 44 d
How we counted: 1052 open Process Engineering (Semiconductor Process) roles from 56 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.
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