Prinicipal DFT Engineer - Irvine, California, United States
$230,000 - $275,000 USD yearly
Originally posted 16 September 2026 by the employer — open 0 days.
About the role
This role involves implementing robust Design-for-Test methodologies that enable high quality, high volume production of complex ASIC and SoC products.
What you'll do
- Develop and implement DFT architecture for ASIC and SoC designs.
- Perform scan insertion, scan chain planning, and scan compression implementation.
- Generate and validate ATPG patterns and analyze fault coverage results.
- Implement and verify MBIST and other on-chip test features.
- Collaborate with RTL, verification, and physical design teams to ensure successful DFT integration.
- Support JTAG and boundary-scan implementation and debug.
- Drive DFT signoff activities and manufacturing test readiness.
- Participate in silicon bring-up, failure analysis, and yield improvement efforts.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
- 8+ years of ASIC/SoC DFT experience.
- Strong understanding of scan, ATPG, fault models, and test coverage methodologies.
- Experience with Synopsys TestMAX/TetraMAX, DFT Compiler, Siemens Tessent, Cadence Modus, or equivalent tools.
- Knowledge of Verilog/SystemVerilog and digital design fundamentals.
- Experience in Linux and scripting using Python, Tcl, Perl, or Shell.
- Strong debugging abilities.
Nice to have
- Experience with advanced-node semiconductor technologies.
- Hands-on experience with MBIST, compression architectures, and JTAG.
- Knowledge of timing closure, physical design impacts, and low-power design techniques.
- Experience supporting silicon validation and manufacturing production ramps.
This role has been open 0 days — well below the 64-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
214
|
Median days open
64 d
|
Median salary
$196k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Celero | All employers we track in this specialty (214 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 214 |
| Open roles in the wider Digital Design & Verification family | 5 | 3004 · 116 employers |
| Median days open | 0 d | 64 d (−64 d vs this employer) |
| Median salary (USD postings) | — | $196k |
Who's hiring in this category
- AMD · 37 open roles · median 42 d
- Qualcomm · 20 open roles · median 77 d
- NVIDIA · 19 open roles · median 64 d
- NXP Semiconductors · 14 open roles · median 78 d
- Micron Technology · 10 open roles · median 107 d
- Intel Corporation · 9 open roles · median 56 d
How we counted: 214 open DFT Engineering (DFT Test) roles from 48 employers tracked in the SemiconductorJobs index, counted 16 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.