Principle DFT Engineer - Bangalore, India
Originally posted 28 September 2026 by the employer.
This role focuses on DFT in products catering to the networking domain, including Optical Digital Signal Processing (ODSP), Active Electrical Cable (AEC), and Coherent Digital Signal Processing (CDSP).
About the role
This role involves defining and driving DFT architecture and test strategy for complex IPs and SoCs within the Connectivity Business Unit DFT team. The work focuses on networking domain products such as Optical Digital Signal Processing (ODSP), Active Electrical Cable (AEC), and Coherent Digital Signal Processing (CDSP).
What you'll do
- Define and drive DFT architecture and test strategy for complex IPs and SoCs, ensuring robust testability and alignment with product goals.
- Lead the implementation and integration of Scan, ATPG, JTAG, MBIST, and Boundary Scan (BSCAN) solutions, ensuring compliance with IEEE 1149.1/1149.6 standards.
- Develop and deploy DFT features including test structures, IP-level DFT integration, ATPG fault models, test point insertion, coverage optimization, scan insertion, and MBIST implementation.
- Own and execute hierarchical DFT flows across the design hierarchy, from individual IPs through full-chip integration.
- Generate and validate production test patterns, perform RTL and netlist verification, execute gate-level simulations (zero-delay and SDF-based), and ensure comprehensive test-mode validation.
- Drive Post-Silicon bring-up, ATE debug, silicon characterization, and production ramp-up activities, enabling efficient silicon validation and productization.
What you'll need
- Master’s degree or PhD in Computer Science, Electrical Engineering, or related fields with 12+ years of experience, or Bachelor's degree in Electronics, Electrical Engineering, or related fields with 14+ years of professional experience.
- Hands-on working experience in DFT-Execution, SCAN-Insertion, MBIST, ATPG, Validation, STA, IP-DFX, Post-Silicon Bring up, and Debug.
- Thorough knowledge of various DFT/Test architecture solutions and involvement in DFT-Architecture definition of at least two designs.
- Strong fundamentals in Digital Circuit Design and Logic Design.
- Understanding of DFT Flows and Methodologies.
- Experience with Cadence/Mentor/Synopsys Tool set (Genus, Modus, NCSim, DC, Tessent, Spyglass, Tmax).
- Proven experience leading DFT activities, including technical leadership, mentoring, and guiding DFT engineers.
- Experience owning complete DFT responsibility for one or more successful chip tapeouts.
Nice to have
- Scripting skills in Perl.
- Scripting skills in Tcl for flow automation.
This role has been open 0 days — well below the 63-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
220
|
Median days open
63 d
|
Median salary
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (220 roles · 50 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 220 |
| Open roles in the wider Digital Design & Verification family | 28 | 3070 · 114 employers |
| Median days open | 10 d | 63 d (−53 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 38 open roles · median 35 d
- Qualcomm · 23 open roles · median 87 d
- NXP Semiconductors · 21 open roles · median 80 d
- NVIDIA · 15 open roles · median 75 d
- Synopsys · 9 open roles · median 20 d
- Intel Corporation · 8 open roles · median 59 d
How we counted: 220 open DFT Engineering (DFT Test) roles from 50 employers tracked in the SemiconductorJobs index, counted 28 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.