Principal Verification Engineer - San Jose, California, United States
$185,000 - $230,000 USD yearly
Originally posted 26 October 2026 by the employer.
About the role
Astera Labs is seeking a Principal Verification Engineer to develop verification methodologies and drive full-lifecycle functional verification for complex ASICs. The role focuses on verification strategy and execution for SoCs targeting server and networking applications.
What you'll do
- Lead the functional verification of ASICs, including test planning, development, execution, and coverage analysis. - Apply directed and constrained-random verification techniques using SystemVerilog/UVM and relevant tools. - Collaborate with software and system validation teams to create and execute test plans on emulation platforms. - Debug test failures, analyze coverage results, and close functional coverage gaps. - Work with RTL designers to troubleshoot and resolve design issues. - Drive verification strategy and methodology for SoCs in server and networking applications.
What you'll need
- Bachelor’s degree in Electrical Engineering. - 8+ years of experience in SoC verification, particularly for server and networking applications. - Expertise in SystemVerilog/UVM and hands-on experience across the full verification lifecycle. - Proficiency with industry-standard simulators, version control, and regression systems. - Experience developing and executing test sequences, generating stimuli, and identifying verification holes. - Familiarity with verification of switching architectures, including packet processing and forwarding engines.
Nice to have
- Master's degree in Electrical Engineering. - Experience with third-party Verification IP for protocols such as PCIe, Ethernet, and InfiniBand. - Background in Network-on-Chip (NoC) architectures for smart NICs and AI accelerators. - Knowledge of Ethernet/PCIe switching and central buffer architectures. - Experience with emulation platforms and hardware-software co-verification.
Skills: SystemVerilog, UVM, functional verification, coverage analysis, ASIC
This role has been open 0 days — well below the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1254 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 1254 |
| Open roles in the wider Digital Design & Verification family | 60 | 3345 · 116 employers |
| Median days open | 84 d | 66 d (+18 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, functional verification, coverage analysis, ASIC
Who's hiring in this category
- Qualcomm · 118 open roles · median 45 d
- AMD · 92 open roles · median 55 d
- NVIDIA · 91 open roles · median 65 d
- Synopsys · 65 open roles · median 41 d
- SiFive · 55 open roles · median 83 d
- Cadence Design Systems · 52 open roles · median 125 d
How we counted: 1254 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.