Principal Test Development Engineer - Santa Clara, CA, United States
Originally posted 22 September 2026 by the employer — open 0 days.
Test features on silicon semiconductor chips using the Advantest 93K tester platform.
About the role
This role involves developing and optimizing test programs and hardware for silicon semiconductor chips to ensure product specifications are met. You will work with the Advantest 93K tester platform to validate chip features and ensure quality.
What you'll do
- Develop test programs on the Advantest 93K tester platform.
- Design tester hardware for high-speed testing.
- Create documentation for detail test plans and test methodologies.
- Convert test patterns from design simulation environments to ATE format.
- Play a lead role in test flow optimization, test time reduction, and yield improvement.
- Release production test programs in collaboration with product engineers.
What you'll need
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 5-10 years of related professional experience.
- Minimum 6+ years of test program development experience on the Advantest 93K ATE tester platform.
- Demonstrable experience in ATE testing, test methodology, silicon process, DFT/DFM, and high-speed digital testing.
- 4+ years experience with C/C++, Perl, Python, and Linux environment.
Nice to have
- Master's degree in Computer Science, Electrical Engineering or related fields with 3-5 years of experience.
This role has been open 0 days — well below the 25-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
418
|
Median days open
25 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (418 roles · 68 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 418 |
| Open roles in the wider Silicon Validation & Test family | 37 | 2063 · 112 employers |
| Median days open | 0 d | 25 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Teradyne · 51 open roles · median 4 d
- Infineon Technologies · 37 open roles · median 31 d
- Renesas Electronics · 33 open roles · median 32 d
- Micron Technology · 27 open roles · median 22 d
- Qualcomm · 24 open roles · median 20 d
- AMD · 19 open roles · median 28 d
How we counted: 418 open Silicon Test Engineering (DFT Test) roles from 68 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.