Principal Test Architect – AI & Advanced Test Technology - Austin, United States
Originally posted 29 September 2026 by the employer. Relisted by the employer on 19 October 2026.
About the role
This role defines and drives semiconductor test technology and methodologies, focusing on AI-enabled test development, simulation platforms, and Design for Testability (DFT).
What you'll do
- Define and drive advanced test technology and methodology roadmaps across product lifecycles. - Develop AI-enabled solutions to improve test development, debug, and validation efficiency. - Lead the development of simulation and virtual test environments to enable earlier test readiness. - Drive DFT strategy, test coverage improvement, and testability requirements for new products while partnering with design teams. - Create reusable frameworks, tools, and automation to reduce development cycle time. - Provide technical leadership and mentorship across global engineering teams.
What you'll need
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field. - 10+ years of semiconductor Test Engineering, Product Engineering, DFT, or Test Architecture experience. - Expertise in ATE test development and production test methodologies. - Understanding of DFT concepts including scan, ATPG, memory test, structural test, and diagnostics. - Experience developing software tools and automation solutions using Python and related technologies. - Knowledge of AI/ML applications, simulation environments, and data-driven engineering workflows.
Nice to have
- Experience developing AI-assisted engineering tools. - Experience with virtual test, digital twin, or simulation-based validation methodologies. - Background in analog, mixed-signal, power, or digital semiconductor products. - Experience influencing engineering standards and technology strategy across multiple product lines.
This role has been open 20 days — well below the 31-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
550
|
Median days open
31 d
|
Median salary
$173k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (550 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 45 | 550 |
| Open roles in the wider Silicon Validation & Test family | 116 | 2227 · 113 employers |
| Median days open | 25 d | 31 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $173k |
Who's hiring in this category
- Teradyne · 75 open roles · median 25 d
- Renesas Electronics (this employer) · 43 open roles · median 25 d
- Infineon Technologies · 41 open roles · median 41 d
- Micron Technology · 29 open roles · median 35 d
- Qualcomm · 28 open roles · median 31 d
- Texas Instruments · 23 open roles · median 26 d
How we counted: 550 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.