Principal System Debug Engineer - TX, Austin, United States
Originally posted 9 September 2026 by the employer.
This role focuses on system-level debug of advanced microprocessors.
About the role
As a Principal System Debug Engineer, you will lead the system-level debug of advanced microprocessors within complex customer applications and system design environments, acting as a critical bridge between internal silicon/software engineering teams and OEM, ODM, and Hyperscaler customers.
What you'll do
- Lead the triage, investigation, and root-cause analysis of complex system-level issues involving CPU silicon, platform hardware, firmware, drivers, and OS/hypervisor interactions in customer environments.
- Serve as the primary technical liaison for strategic customers, guiding them through platform design, debug methodologies, and issue resolution.
- Partner with internal Silicon Design, Architecture, Firmware (BIOS/UEFI/BMC), OS/Kernel, and Validation teams to drive systemic fixes and influence future CPU architectures.
- Act as the technical task force leader during critical customer escalations, providing executive updates and driving technical action plans.
What you'll need
- Deep technical expertise in CPU architecture, high-speed I/O interfaces, firmware/BIOS, system software, drivers, OS/kernels, software stacks, platform hardware design, signal integrity, and power integrity.
- Extensive system-level debug experience.
- Strong processor architecture, hardware, and software expertise.
- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Nice to have
- Deep, foundational knowledge of modern CPU architectures (x86 mandatory), including pipelines, cache coherency, memory controllers, power management (C-states, P-states), RAS features, MCA (Machine Check Architecture), SoC and platform security features, RoT (root-of-trust).
- Extensive expertise in the architecture and protocol-level debug of high-speed I/O interfaces, including PCIe (Gen 4/5/6), CXL, DDR4/DDR5, Ethernet, USB, and low-speed buses (I2C, SPI, I3C, eSPI).
- Strong understanding of the full system software stack, including BIOS/UEFI, BMC/IPMI, Linux/Windows kernel internals, device drivers, and hypervisors (KVM, VMware, Hyper-V).
- Solid grasp of system-level hardware design, including board schematics, PCB layout, power delivery networks (VRMs), clocking, and signal integrity fundamentals.
- Proven track record of performing complex system bring-up and debug using hardware tools (JTAG/ITP debuggers, oscilloscopes, logic analyzers, protocol analyzers) and software debuggers (GDB, WinDbg, kernel panics/crash dump analysis).
- Experience working directly with Cloud Service Providers (Hyperscalers) and Tier-1 Server/Client OEMs.
- Proficiency in scripting and programming languages (Python, C, C++) for test automation and debug tool development.
- Hands-on expertise in debugging hardware (system bring-up, signal integrity, power integrity issues) and debugging firmware/software running on actual hardware platforms.
- Experience with RAS (Reliability, Availability, and Serviceability) architecture and machine check exception (MCE) analysis.
Skills: system-level debug, CPU architecture, high-speed I/O interfaces, platform hardware design, firmware/BIOS
This role has been open 35 days — well below the 55-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · SOC Architecture
|
Open roles in category
107
|
Median days open
55 d
|
Median salary
$212k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (107 roles · 28 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 107 |
| Open roles in the wider Software, Firmware & Systems family | 404 | 6145 · 145 employers |
| Median days open | 55 d | 55 d (same as this employer) |
| Median salary (USD postings) | — | $212k |
Skills observed across this category: system-level debug, CPU architecture, high-speed I/O interfaces, platform hardware design, firmware/BIOS
Who's hiring in this category
- AMD (this employer) · 29 open roles · median 55 d
- Qualcomm · 21 open roles · median 43 d
- NVIDIA · 16 open roles · median 74 d
- Intel Corporation · 7 open roles · median 42 d
- Mobileye · 4 open roles · median 22 d
- Apple · 3 open roles · median 14 d
How we counted: 107 open Hardware Systems Engineering (SOC Architecture) roles from 28 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.