Principal (STA/ Sign-Off) Engineer-17042 (Austin/ Sunnyvale)
Originally posted 17 June 2026 by the employer.
Work on SerDes and Memory interface controllers, PHYs, and subsystems within the Interface IP Digital Design Methodology team.
About the role
As a member of the IP Digital Design Methodology team, you will define ASIC design standards and flows and assist IP development teams. You will work on SerDes and Memory interface controllers, PHYs, and subsystems.
What you'll do
- Develop and deploy advanced node signoff methodologies for IP designs targeting different foundries. - Drive PPA for IP designs alongside development teams. - Evaluate and exercise development flow components including signoff timing, power, physical verification, EM/IR analysis, and ECOs. - Develop and maintain digital design methodologies, including documentation, scripts, and training materials. - Serve as a liaison between Synopsys tool and IP design teams. - Continuously refine design processes to enhance efficiency and performance.
What you'll need
- BS or MS in EE with 12+ years of hands-on experience developing CAD flows for high-speed digital IP cores and/or SOCs. - Direct hands-on experience enabling advanced node STA/ Timing signoff flows at SoC level. - Knowledge of IP deliverables, ASIC implementation and physical design flow and tools, memories, logic libraries, and PDK versions.
Nice to have
- Familiarity with EMIR & Thermal sign-off flows. - Familiarity with other Synopsys tools such as StarRC and ICV. - Working knowledge of high-speed interface protocols such as HDMI, MIPI, PCIe, SATA, Ethernet, USB, DP, and DDR.
This role has been open 125 days — well above the 70-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
696
|
Median days open
70 d
|
Median salary
$193k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (696 roles · 76 employers) |
|---|---|---|
| Open roles in this specialty | 61 | 696 |
| Open roles in the wider Physical Implementation family | 106 | 1487 · 110 employers |
| Median days open | 41 d | 70 d (−29 d vs this employer) |
| Median salary (USD postings) | — | $193k |
Who's hiring in this category
- Cadence Design Systems · 155 open roles · median 150 d
- Synopsys (this employer) · 63 open roles · median 41 d
- Micron Technology · 46 open roles · median 50 d
- GlobalFoundries · 38 open roles · median 24 d
- Qualcomm · 37 open roles · median 74 d
- Keysight Technologies · 34 open roles · median 77 d
How we counted: 696 open EDA/CAD Engineering (EDA Tools) roles from 76 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.