Principal Solutions Architect – Semiconductor Test
Lead technical test development strategy across Advantest V93000 and Teradyne UltraFLEX ATE platforms from wafer probe to final test.
Originally posted 30 October 2026 by the employer. Relisted by the employer on 31 October 2026.
About the role
This role defines and leads the technical strategy for semiconductor test, covering wafer and package test operations from start to finish. You will establish the architectural vision for device testing across wafer probe and final package test while partnering with development, process, product engineering, and manufacturing teams.
What you'll do
- Define the comprehensive test development strategy across wafer-level (probe/ATE) and package/final/qual test for product families.
- Lead architectural trade-off decisions on test coverage, test time, cost of test, and quality escapes across the full test flow.
- Establish architectural guidelines for test programs, Test Methods/Class structures, modularity, and reuse across ATE platforms such as Advantest and Teradyne.
- Serve as the senior liaison between build and test engineering for DFT architecture decisions including scan, BIST, JTAG, boundary scan, and embedded compression.
- Drive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization.
- Define test roadmaps aligned to device technology roadmaps and engage with ATE vendors, test IP providers, and industry consortia (SEMI, JEDEC, IEEE).
What you'll need
- 15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
- MSEE, MSCE, MSCS, or related field (or equivalent experience).
- Extensive knowledge in at least three of the following areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
- Skilled in ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar systems.
- Strong background in DFT architectures including scan compression, MBIST, LBIST, and JTAG.
- Proficiency in test-related scripting and automation with Python, Perl, C++, or platform-native languages.
More semiconductor jobs: NVIDIA jobs · Test engineer jobs · California jobs
This role has been open 151 days — well above the 122-day median for Silicon Test Engineering roles.
Silicon Test Engineering · Silicon Validation
|
Open roles in category
165
|
Median days open
122 d
|
Category median salary (all employers)
$136k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (165 roles · 54 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 165 |
| Open roles in the wider Silicon Validation & Test family | 99 | 2317 · 111 employers |
| Median days open | 98 d | 122 d (−24 d vs this employer) |
| Median salary (USD postings) | — | $136k |
Who's hiring in this category
- Renesas Electronics · 11 open roles · median 113 d
- Teradyne · 11 open roles · median 131 d
- Qualcomm · 10 open roles · median 120 d
- Infineon Technologies · 9 open roles · median 128 d
- Marvell Technology · 9 open roles · median 128 d
- onsemi · 7 open roles · median 120 d
How we counted: 165 open Silicon Test Engineering (Silicon Validation) roles from 54 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.