Principal Signal and Power Integrity Engineer - Shanghai Shi, China
Originally posted 18 September 2026 by the employer — open 0 days.
About the role
This role involves designing complicated PCB layouts across multiple fields including high-speed interfaces, power, and high-density interconnect. You will work on connectivity products for Artificial Intelligence and Machine Learning applications, specifically integrating CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
What you'll do
- Design complicated PCB layouts across high-speed interfaces, power, and high-density interconnect.
- Manage the full PCB design process from feasibility study to DFM and Gerber release.
- Achieve layout design for signal integrity, power integrity, DFT, and DFM.
- Collaborate with the electrical design community to develop systems.
- Execute intense design work in a dynamic environment.
What you'll need
- 10+ years of experience designing complex PCBs (40,000+ pins, 30+ layer count) across high-speed differential pairs, RF, high-power, high-density interconnect (HDI).
- Proficiency in PCB designs with PCIe Gen5/6, Ethernet 112G/224G PAM4, and DDR4/5 applications.
- Proficiency in advanced PCB technologies such as micro-vias, blind vias, any layer HDI, back-drilling, sequential lamination, and step gold finger.
- Master of EDA tools including Cadence Allegro, Polar SI9000, CAM350 or similar DFM inspection tools, and AutoCAD.
- Proficiency in PCB design rules, constraint manager, and checklists.
- Familiarity with PCB manufacture and PCB assembly processes, capable of handling PCB/PCBA EQ.
Skills: PCB layout, high-speed interfaces, signal integrity, power integrity, Cadence Allegro
This role has been open 0 days — well below the 109-day median for Hardware Systems Engineering roles.
Hardware Systems Engineering · Serdes Highspeed
|
Open roles in category
84
|
Median days open
109 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (84 roles · 33 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 84 |
| Open roles in the wider Software, Firmware & Systems family | 12 | 5833 · 143 employers |
| Median days open | 14 d | 109 d (−95 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: PCB layout, high-speed interfaces, signal integrity, power integrity, Cadence Allegro
Who's hiring in this category
- NVIDIA · 12 open roles · median 162 d
- Qualcomm · 12 open roles · median 162 d
- AMD · 10 open roles · median 73 d
- Keysight Technologies · 7 open roles · median 111 d
- Broadcom · 3 open roles · median 172 d
- Lightmatter · 3 open roles · median 79 d
How we counted: 84 open Hardware Systems Engineering (Serdes Highspeed) roles from 33 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.