Principal SerDes Bring-up Validation Engineer - San Jose, California, United States
$185,000 - $240,000 USD yearly
Originally posted 31 July 2026 by the employer. Relisted by the employer on 5 October 2026.
About the role
This role involves leading end-to-end post-silicon bring-up, validation, and characterization. The work focuses on connectivity solutions that integrate CXL, Ethernet, NVLink, PCIe, and UALink semiconductor-based technologies.
What you'll do
- Design, develop, and execute end-to-end post-silicon bring-up and characterization plans.
- Participate in architecture and design-spec reviews to ensure testability and influence design tradeoffs.
- Lead hands-on silicon block level bring-up, functional and parametric testing, and performance benchmarking.
- Build and maintain automation frameworks for scalable test automation, data capture, and analysis.
- Debug and optimize system performance, diagnosing complex failures and performance bottlenecks.
- Root-cause cross-domain failures using lab measurements, waveform analysis, and system-level tests.
- Develop robust Python test scripts and control interfaces for DSP and hardware platforms.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- 8-12 years of hands-on experience in mixed-signal, high-speed lab environments executing characterization and validation.
- Experience with protocol analyzers, BERTs, real-time oscilloscopes, sampling scopes, TDRs, and VNAs.
- Proven track record in post-silicon validation and bring-up of high-speed PHYs or retimers.
- Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization).
- Ability to investigate jitter sources, CDR/PLL behavior, crosstalk, and power integrity issues.
- Practical experience bringing up and debugging retimers, including equalization tuning, pass-through operation, clocking strategies, and reset and link sequencing.
- Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.
Nice to have
- MS or PhD in Electrical Engineering or a related field.
This role has been open 66 days — well above the 41-day median for Post-Silicon Validation roles.
Post-Silicon Validation · Silicon Validation
|
Open roles in category
384
|
Median days open
41 d
|
Median salary
$175k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (384 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 384 |
| Open roles in the wider Silicon Validation & Test family | 21 | 2199 · 110 employers |
| Median days open | 140 d | 41 d (+99 d vs this employer) |
| Median salary (USD postings) | — | $175k |
Who's hiring in this category
- AMD · 54 open roles · median 50 d
- Micron Technology · 41 open roles · median 32 d
- Qualcomm · 30 open roles · median 30 d
- NVIDIA · 21 open roles · median 29 d
- Graphcore · 19 open roles · median 107 d
- Microchip Technology · 18 open roles · median 64 d
How we counted: 384 open Post-Silicon Validation (Silicon Validation) roles from 63 employers tracked in the SemiconductorJobs index, counted 6 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.