Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet - Taipei, Taiwan
Originally posted 14 September 2026 by the employer — open 0 days.
About the role
This role involves leading the verification of connectivity IPs and SoCs powering AI and cloud infrastructure, with a focus on CXL, PCIe, and Ethernet protocols.
What you'll do
- Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon.
- Define verification methodologies, reusable verification frameworks, and best practices.
- Architect and develop scalable UVM/System Verilog verification environments.
- Develop constrained-random, coverage-driven verification methodologies.
- Debug complex RTL, protocol, timing, and integration issues.
- Mentor and coach verification engineers.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field.
- Minimum 10+ years (Principal) or 15+ years (Senior Principal) of experience in Design Verification.
- Strong expertise in System Verilog and UVM.
- Extensive experience in verification planning, execution, and sign-off.
- Deep understanding of constrained-random verification and coverage-driven methodologies.
- Strong experience with assertions (SVA), functional coverage, and protocol compliance.
- Excellent debugging skills involving RTL, simulation, protocol analysis, and waveform debugging.
- Experience with industry-standard simulators such as Synopsys VCS, Cadence Xcelium, or Siemens Questa.
Nice to have
- Experience in CXL Cache, Memory, and I/O protocols.
- Experience in PCIe Transaction, Data Link, and Physical Layers.
- Experience in Ethernet MAC/PCS/PMA architecture.
- Experience in Coherency protocols.
- Experience in High-speed interconnects.
- Experience in AI accelerator connectivity.
- Experience in Data center SoC architecture.
- Experience in Multi-chip and chiplet-based systems.
- Experience in Performance verification.
- Experience in Low-power verification.
- Experience in CDC/RDC verification.
- Experience in Formal Verification.
- Experience in Portable Stimulus (PSS).
- Experience in Python, Perl, Tcl, or similar scripting languages.
- Experience in Emulation and FPGA prototyping.
- Experience leading verification for large SoCs or complex connectivity IPs.
- Proven success delivering multiple first-pass silicon programs.
- Experience with AI infrastructure, cloud networking, or hyperscale data center technologies.
- Familiarity with customer-facing debug and post-silicon issue resolution.
- Contributions to verification methodology, reusable frameworks, or industry standards.
Skills: Design Verification, UVM/System Verilog, CXL, PCI Express, Ethernet
This role has been open 0 days — well below the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1146
|
Median days open
57 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1146 roles · 91 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 1146 |
| Open roles in the wider Digital Design & Verification family | 49 | 3096 · 115 employers |
| Median days open | 71 d | 57 d (+14 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: Design Verification, UVM/System Verilog, CXL, PCI Express, Ethernet
Who's hiring in this category
- Qualcomm · 105 open roles · median 53 d
- AMD · 102 open roles · median 28 d
- NVIDIA · 89 open roles · median 63 d
- Micron Technology · 53 open roles · median 98 d
- Arm Holdings · 49 open roles · median 70 d
- Marvell Technology · 49 open roles · median 116 d
How we counted: 1146 open Design Verification (Design Verification) roles from 91 employers tracked in the SemiconductorJobs index, counted 15 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.