Principal Power Design Engineer - Palo Alto, United States
$160,000 - $240,000 USD yearly
Originally posted 6 July 2026 by the employer — open 74 days.
About the role
This role involves owning the design, implementation, and validation of power delivery systems that support high-performance AI compute hardware. You will design and test multi-phase voltage regulators, point-of-load converters, and sequencing circuitry for systems under demanding, dynamic AI inference workloads.
What you'll do
- Own hardware schematic design for multi-phase buck regulators, point-of-load converters, and power sequencing circuitry.
- Select critical power components, including passives, inductors, power stages, controllers, and supporting circuitry.
- Define placement and routing constraints for board-level power delivery networks.
- Lead lab validation of power subsystems, including VRM efficiency, loop stability, DC IR drop, thermal behavior, and transient response.
- Use oscilloscopes, electronic loads, network analyzers, and thermal cameras to characterize power rails under dynamic load conditions.
- Debug power integrity issues across board, package, silicon, firmware, workload, and system-level interactions.
What you'll need
- Extensive experience designing high-current, multi-phase DC-DC regulators for high-power ASICs, GPUs, processors, accelerators, or similar compute platforms.
- Strong background in power hardware design for systems with 500W+ devices or comparable high-current power delivery requirements.
- Deep understanding of board-level PDN (power delivery network) implementation, decoupling strategy, power sequencing, transient response, and voltage regulation.
- Hands-on experience with schematic capture and layout oversight for complex power delivery systems, preferably using Cadence Allegro or Concept.
- Strong lab validation skills using electronic loads, oscilloscopes, network analyzers for loop stability testing, thermal cameras, and related power measurement equipment.
- Proficiency with SPICE-based time-domain circuit simulation or similar power simulation workflows.
Nice to have
- Experience with power delivery for AI accelerators, GPUs, networking ASICs, switch ASICs, or high-performance server platforms.
- Familiarity with power integrity interactions affecting high-speed SerDes, PCIe, Ethernet, CXL, or other sensitive interfaces.
- Experience validating power systems under real workload conditions, including dynamic AI inference or high-utilization compute workloads.
- Exposure to package-level power delivery, socket interfaces, or advanced board/package co-design.
- Experience developing automated lab validation flows using Python or similar scripting languages.
Skills: multi-phase buck regulators, power delivery networks, transient response, power integrity, lab validation
This role has been open 57 days — well below the 70-day median for Power Electronics roles.
Power Electronics · Power Management
|
Open roles in category
71
|
Median days open
70 d
|
Median salary
$169k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Delos Data | All employers we track in this specialty (71 roles · 25 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 71 |
| Open roles in the wider Analog & Mixed-Signal family | 3 | 1339 · 105 employers |
| Median days open | 57 d | 70 d (−13 d vs this employer) |
| Median salary (USD postings) | — | $169k |
Skills observed across this category: multi-phase buck regulators, power delivery networks, transient response, power integrity, lab validation
Who's hiring in this category
- Renesas Electronics · 15 open roles · median 74 d
- Qualcomm · 8 open roles · median 37 d
- Analog Devices · 6 open roles · median 80 d
- Monolithic Power Systems · 6 open roles · median 183 d
- AMD · 5 open roles · median 88 d
- Infineon Technologies · 5 open roles · median 71 d
How we counted: 71 open Power Electronics (Power Management) roles from 25 employers tracked in the SemiconductorJobs index, counted 19 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.