Principal PCIe Subsystem Verification Engineer - Austin, Texas, United States
$249,900 - $338,100 USD yearly
Originally posted 22 July 2026 by the employer.
About the role
Arm's Solutions Engineering team is looking for PCIe and CXL experts to verify the functionality and performance of high-speed IOs at the subsystem level. The team develops silicon solutions targeting mobile, infrastructure, IoT, and automotive applications using 3nm nodes and 3D packaging.
What you'll do
- Execute subsystem integration verification, IO virtualization scenario verification with Arm SMMU, interoperability verification with Arm and third-party IPs, and PCIe/CXL performance verification. - Review architecture and design specifications to construct functional verification strategies. - Author test plans, develop SystemVerilog, Verilog, and UVM testbenches and tests, and debug test failures. - Develop and enhance verification methodologies utilized across the engineering team. - Collaborate with cross-functional teams on design microarchitecture, verification methodologies, and system performance. - Partner with project management on planning and schedules while guiding and supporting junior team members.
What you'll need
- Bachelor's or Master’s degree in Computer Science, Electrical/Computer Engineering, or a related field with 5+ years of experience verifying PCIe or CXL subsystems or SoCs. - Solid understanding of digital hardware design and Verilog HDL. - Experience with PCIe, CXL, and IDE feature verification alongside performance analysis. - Working knowledge of System Memory Management Unit (SMMU) and Generic Interrupt Controller (GIC) integration with PCIe. - Hands-on experience with PCIe and CXL IPs, emulation-friendly transactors, simulation platforms, and emulation platforms. - Expertise in UVM-based verification methodologies and debugger-based failure analysis. - Understanding of verification strategies including test plan creation, task tracking, coverage closure, verification sign-off, and formal methodology.
Nice to have
- Experience with Arm-based designs or ARM System Architectures. - Experience with clock domain crossing verification. - Experience with power-aware verification. - Experience with Perl, Python, or other scripting languages. - Experience with AI tools such as Codex.
Skills: PCIe, CXL, Sub-System integration verification, UVM, SystemVerilog, test plans
This role has been open 88 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1201
|
Median days open
66 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1201 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 49 | 1201 |
| Open roles in the wider Digital Design & Verification family | 104 | 3224 · 116 employers |
| Median days open | 104 d | 66 d (+38 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: PCIe, CXL, Sub-System integration verification, UVM, SystemVerilog, test plans
Who's hiring in this category
- Qualcomm · 110 open roles · median 40 d
- AMD · 95 open roles · median 52 d
- NVIDIA · 84 open roles · median 60 d
- Synopsys · 64 open roles · median 34 d
- SiFive · 55 open roles · median 76 d
- Cadence Design Systems · 50 open roles · median 118 d
How we counted: 1201 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.