Principal PCB - Package co-design Architect - Chandler, Arizona, United States

Originally posted 10 August 2026 by the employer.

This role focuses on prototyping Arm's latest IP products to build physical hardware development platforms based around custom Arm SoC.

About the role

This role involves specializing in PCB to silicon packaging co-design and system-level hardware architecture within Arm's Packaging, Boards and Multiphysics team. You will work with the wider business, collaborating with SoC teams, architects, and platform leads.

What you'll do

• Collaborate with engineering groups to specify, evaluate, analyze, and develop solutions for efficient PCB and silicon package integration.
• Drive PCB development alongside the chip packaging team, including brainstorming breakout, routing strategies, design rules, and layer optimization.
• Engage with technical leads and SoC development teams to translate technology requirements into platform architectures.
• Communicate technical concepts clearly and credibly across audiences ranging from Silicon and Packaging architecture to technology leads.
• Provide timescale estimates and justifications into the program team.

What you'll need

• Deep technical background and understanding of SoC architectures and platforms involving high-performance embedded compute, Cloud/Edge AI, IoT space.
• Experience with various high-speed IO interface standards (e.g. PCIe Gen5/6/7, LPDDR5/6, CSI, DSI) and peripherals for embedded storage and compute systems.
• Competence with embedded system board design, with complex LSI devices such as FPGAs and embedded firmware and power management ICs (PMICs).
• Familiarity with different IC packaging technologies and their impact on PCB design to ensure seamless integration of SoCs.
• Experience of collaborating with chip packaging teams. Ability to influence and drive SoC device pin-outs for cost optimization, routing feasibility, and layer trade-off analysis.
• Expertise in escape routing analysis of high density SoCs and able to provide estimates of the IO count that can be routed with a particular stack-up and design rule set.
• Extensive knowledge of Signal and Power Integrity analysis techniques from both board design and chip packaging perspectives.
• Understanding of the PCB fabrication process (PTH and HDI), stackup/VIA topologies, and substrate materials.
• Ability to collaborate with PCB fabricators and CEM partners to assess manufacturability of advanced PCB technologies.
• Evaluate package pinout options against PCB routability, SI/PI performance, layer count, manufacturability, and cost.
• Ability to define or review PCB layout guidelines and constraints.
• Support early silicon and board architecture definition, including component placement, form-factor constraints, PDN strategy, and routing feasibility.
• Proficiency in the use of EDA tools for schematic entry and PCB layout (Cadence OrCAD & Allegro).