Principal Package Design Engineer - San Jose, United States

Originally posted 24 July 2026 by the employer. Relisted by the employer on 26 September 2026.

About the role

The Principal Package Design Engineer leads the development and integration of packaging solutions for high-performance semiconductors and electronic products within the Semiconductor Power Product Group. The role focuses on advanced package architecture, assembly processes, thermal and mechanical reliability, and application system integration for AI infrastructure and data center power management.

What you'll do

- Lead the design, development, and qualification of advanced packaging solutions, including flip-chip, chip embedding, WLP/FOWLP, panel-level packaging, 2.5D/3D packaging, SiP, BGA/CSP, and heterogeneous bonding. - Define package architecture based on electrical, thermal, mechanical, reliability, and cost requirements using hands-on simulation tools. - Oversee package layout reviews, stack-up definition, material selection, and interconnect strategy. - Perform and guide simulations covering signal integrity, power integrity, thermal performance, mechanical stress, warpage, and design for manufacturability (DFM). - Develop assembly flows, process requirements, and qualification plans (DOE, failure analysis, reliability testing) with OSATs and manufacturing partners. - Resolve packaging issues during NPI prototype builds, qualification, and production ramp while maintaining package specifications and design rules.

What you'll need

- MSc or PhD degree in Electrical Engineering, Materials Science, Mechanical Engineering, Chemical Engineering, or a related field. - 5+ years of experience in advanced semiconductor packaging or advanced electronics packaging and system integration. - Hands-on knowledge of packaging technologies, materials, assembly processes, and system integration applied to AI infrastructure and data center power management. - Hands-on model setup, simulation, and analysis experience covering thermal, mechanical, and electrical interactions in package design. - Direct experience working with OSATs, substrate vendors, assembly houses, and semiconductor supply chains. - Track record of failure analysis, root cause/corrective action, and package reliability testing and qualification standards.

Nice to have

- Experience with power semiconductor devices and packaging including Si/SiC/GaN MOSFETs, Power Modules, Intelligent Power Modules, and power products in high-performance computing, AI/ML hardware, or mobile products. - Hands-on experience with package design and simulation tools including Cadence Allegro Package Designer, SolidWorks, ANSYS, COMSOL, and JMP / Minitab. - Knowledge of JEDEC standards, IPC standards, and semiconductor qualification methods. - Experience in W2W, D2W, D2D 3D heterogeneous integration and chiplet-based packaging.

Skills: advanced semiconductor packaging, 2.5D/3D packaging, package layout reviews, signal integrity, thermal performance