Principal Memory Subsystem Architect - GA, Home Office, United States
Digital Design & SoC Architecture
Originally posted 3 October 2026 by the employer.
Own AMD’s architecture strategy for low-power DRAM and advanced memory-buffer technologies.
About the role
This Principal Memory Subsystem Architect defines AMD’s architecture strategy for low-power DRAM and advanced memory-buffer technologies, leading technical positions for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, and future buffer architectures.
What you'll do
- Own AMD’s multi-generation LPDDR and DRAM-buffer architecture strategy across business units and product generations.
- Lead AMD technical positions and serve as the company-wide authority for LPDDR devices and advanced DRAM buffers.
- Advance AMD positions in JEDEC through proposals, ballots, negotiations, partnerships, and consensus building.
- Define architectural requirements for LPDDR devices, DDR6 registered clock drivers, LPDDR6 in-package buffers, and future buffer architectures.
- Coordinate DRAM and buffer behavior with controller, PHY, SoC, package, module, board, firmware, validation, and platform requirements.
- Align DRAM vendors and suppliers of buffers, PMICs, regulators, hubs, connectors, and related technologies on roadmaps and qualification plans.
What you'll need
- Deep LPDDR and DDR knowledge.
- Demonstrated ability to align internal teams and external partners around technically rigorous, implementable positions.
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
Nice to have
- Master’s degree or PhD.
Skills: LPDDR, DRAM Buffer, JEDEC, memory architecture, DDR6, in-package buffers