Principal Memory Sub-System Validation Lead - CA, Santa Clara, United States
Originally posted 22 September 2026 by the employer.
Join the team driving validation and characterization of High-Bandwidth Memory (HBM) on AMD’s Datacenter GPU (Machine Instinct product).
About the role
The Principal Memory Sub-System Validation Lead will drive and deliver pre- and post-silicon validation and characterization of on-die High-Bandwidth Memory (HBM) on AMD’s Datacenter GPU (Machine Instinct product). This role is a critical interface between DRAM architecture, Memory Controller Design and DV, DDR PHY, DRAM product engineering, and software teams.
What you'll do
- Plan, execute, and debug all aspects of pre- and post-silicon validation for memory sub-systems. - Develop and execute test plans for HBM Functional and Electrical Validation (PVT Shmoo Characterization). - Drive debug in post silicon, root-cause problems, and steer corrective actions. - Collaborate on memory-related silicon issues across Design, Verification, Silicon Validation, Productization, System Hardware, and Software teams. - Debug post-production issues and customer returns. - Summarize complex technical details for executive reporting.
What you'll need
- Extensive knowledge of high bandwidth memory subsystem, including SoC memory architecture, Unified Memory controller, PHY design, high speed IO interface, DRAM device, and associated calibration/training mechanisms. - Significant experience in DDR, LPDDR, HBM SoC validation, verification, and debug of High-Bandwidth Memory sub-system. - Hands-on experience using industry standard JTAG, I2C, Tester, and Lab tools. - Strong programming skills (C/C++, Python) and comfortable working on Linux or Windows platforms. - Ability to work in a lab environment. - Bachelor's or Master's in Electrical or Computer Engineering.
Nice to have
- Experience working with major DRAM memory vendors and validation of DRAM device. - Experience in developing test cases for Machine Learning, High Performance Computing.
Skills: HBM, post-silicon validation, DDR, LPDDR, debug, characterization