Principal Logic Design Engineer - Bengaluru, Karnataka, India
Originally posted 30 September 2026 by the employer.
Design complex connectivity IPs such as PCIe, UALink, Ethernet, CXL, and UCIe.
About the role
This role involves leading the development of complex IPs/subsystems with technical ownership across architecture, microarchitecture, RTL implementation, integration, and silicon bring-up. You will work on connectivity IPs/subsystems, including Transaction, Data Link, and Physical interface integration.
What you'll do
- Lead RTL/microarchitecture development for complex connectivity IP/subsystems.
- Translate specifications and system requirements into robust hardware architecture.
- Design high-performance and scalable logic for controllers/subsystems.
- Develop and review RTL using SystemVerilog/Verilog.
- Develop robust mechanisms for flow control, ordering, buffering, arbitration, error handling, and reliability.
- Drive performance, latency, area, and power optimization.
- Collaborate with verification teams to develop verification strategies and debug complex failures.
- Work with SoC integration and physical design teams to ensure successful implementation.
- Lead technical reviews and mentor senior engineers.
- Support post-silicon debug and root-cause analysis.
What you'll need
- 10+ years of experience.
- Extensive experience in complex connectivity IPs such as PCIE, UALink, Ethernet, CXL, UCIe.
- Strong RTL design experience using SystemVerilog/Verilog.
- Deep knowledge of PCIe architecture and protocol.
- Strong understanding of high-speed data paths, FIFOs, arbitration, flow control, and error handling.
- Experience with simulation, lint, CDC, synthesis, and timing considerations.
- Strong debugging and problem-solving skills.
Nice to have
- Experience of working in switching silicon.
- Experience of working on entire cycle from concept to silicon production.
Skills: micro-architecture, RTL design, SystemVerilog/Verilog, PCIe architecture, high-speed data paths
This role has been open 27 days — well below the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1081
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1081 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 29 | 1081 |
| Open roles in the wider Digital Design & Verification family | 61 | 3328 · 116 employers |
| Median days open | 46 d | 66 d (−20 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: micro-architecture, RTL design, SystemVerilog/Verilog, PCIe architecture, high-speed data paths
Who's hiring in this category
- Qualcomm · 158 open roles · median 63 d
- Synopsys · 86 open roles · median 40 d
- AMD · 77 open roles · median 45 d
- Analog Devices · 49 open roles · median 56 d
- NXP Semiconductors · 44 open roles · median 100 d
- NVIDIA · 37 open roles · median 52 d
How we counted: 1081 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.