Principal Layout Designer - Hyderabad - Phoenix Aquila, India
Originally posted 21 September 2026 by the employer.
About the role
This role involves understanding design constraints and implementing high-quality layouts for memory and storage solutions. You will be instrumental in the layout of critical Core/Pitch blocks for NAND products.
What you'll do
- Understand design constraints and implement high-quality layouts.
- Create layouts of critical Core/Pitch blocks such as Array, Row decoder, and Column Decoder.
- Deliver major level blocks, including signal and floorplan, to Core/Pitch and Periphery areas.
- Apply multiple layout techniques for the design and verification of Array, Digital, and Analog circuits.
- Execute secondary layout tasks such as ECO, LCO, and DFM.
- Coordinate with TD, Design, CAD, and layout teams to deliver on schedule.
What you'll need
- 10+ years of experience in layout.
- Proficiency using Cadence VXL on periphery blocks.
- Strong debug and problem-solving skills for LVS, DRC & Layout issues.
- Hands-on experience in creating layout of critical Core/Pitch blocks.
- Good understanding of Core/Pitch Layout fundamentals such as BL & WL pitch.
- Experience with Chip Level Integration and Die Size calculations.
- Good understanding of Design rules.
- Experience with NAND product requirements.
- Ability to understand various circuit design protocols, different fab processes, mask generation techniques, and tape-out processes and procedures.
Skills: Cadence VXL, LVS, DRC, Core/Pitch blocks, Chip Level Integration, NAND
This role has been open 13 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: Cadence VXL, LVS, DRC, Core/Pitch blocks, Chip Level Integration, NAND
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.