Principal IC Packaging Engineer
$201,600 - $302,400 USD yearly
Originally posted 9 January 2026 by the employer.
About the role
The Principal IC Packaging Engineer leads the development of integrated circuit packaging technologies from concept through high-volume manufacturing at assembly suppliers. The position targets applications in Data Center AI, Power Management, and emerging markets.
What you'll do
- Lead the development of packaging technologies, including wafer bonding, Redistribution Layer (RDL), 3D, wafer dicing, and 2.5D packaging. - Oversee new product introductions and guide transitions to high-volume manufacturing (HVM). - Define package architecture and high-density interconnect designs while balancing performance, reliability, and cost constraints. - Collaborate with and manage foundries and Outsourced Semiconductor Assembly and Test (OSAT) suppliers across packaging assembly processes, materials, equipment, and design rules. - Lead cross-functional teams to resolve technical challenges during packaging development and manufacturing.
What you'll need
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 8+ years of System/Package Design/Technology Engineering or related work experience (or Master's degree and 7+ years, or PhD and 6+ years). - Direct experience in packaging assembly processes, materials, and equipment covering Redistribution Layer (RDL), wafer bonding, flip chip, wire bond, and System in Package (SiP). - Background managing foundry and OSAT partners to deliver packaging solutions to full-scale production.
Nice to have
- M.S. or Ph.D. in Mechanical, Electrical, or Materials Engineering. - 17+ years of hands-on experience in packaging technology development, specifically in 2.5D/3D for high-density die-to-die (D2D) interconnects, RDL, fan-out bridges, FCBGA, and MCM architectures. - Experience with high-performance computing products, data center and rack design alongside contract manufacturers (CM). - Knowledge of substrate manufacturing processes, design rules, reliability standards, qualification procedures, and failure analysis techniques.
Skills: advanced packaging technologies, wafer bonding, RDL, 3D, 2.5D packaging, high-density die-to-die (D2D) interconnects
This role has been open 200 days — well above the 48-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Advanced Packaging
|
Open roles in category
69
|
Median days open
48 d
|
Median salary
$167k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (69 roles · 24 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 69 |
| Median days open | 89 d | 48 d (+41 d vs this employer) |
| Median salary (USD postings) | — | $167k |
Skills observed across this category: advanced packaging technologies, wafer bonding, RDL, 3D, 2.5D packaging, high-density die-to-die (D2D) interconnects
Who's hiring in this category
- AMD · 10 open roles · median 32 d
- Micron Technology · 9 open roles · median 177 d
- Marvell Technology · 6 open roles · median 22 d
- NVIDIA · 6 open roles · median 47 d
- Broadcom · 4 open roles · median 147 d
- GlobalFoundries · 4 open roles · median 115 d
How we counted: 69 open Chiplet/Advanced Packaging Design (Advanced Packaging) roles from 24 employers tracked in the SemiconductorJobs index, counted 25 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.