Principal, IC Digital Design Engineer - Irvine, CA, United States
Originally posted 14 July 2026 by the employer. Relisted by the employer on 15 July 2026.
About the role
As a Principal, Digital IC Design Engineer at Marvell, you will join the DCE – Connectivity Business Group developing connectivity silicon for AI scale data centers. You will architect and implement digital pipelines, high-speed datapaths, and DSP processing engines for Ethernet and optical interconnects.
What you'll do
- Define SoC-level specifications with systems and architecture teams, covering performance, power, area, and DSP/datapath architectural considerations. - Translate high-level product and protocol requirements into detailed micro-architecture specifications for complex subsystems, high-speed datapaths, DSP pipelines, and IP blocks. - Own RTL development using synthesizable SystemVerilog, meeting functionality, performance, and power targets. - Execute the ASIC front-end design flow, including lint, CDC/RDC, synthesis, timing constraint development, and design-for-test readiness. - Partner with STA and PNR teams to support timing closure, floorplanning, congestion analysis, and design optimizations across advanced process nodes. - Lead integration of digital logic into subsystems and top-level assemblies, and support DV test planning, emulation, FPGA prototyping, and post-silicon bring-up.
What you'll need
- 12+ years of industry experience working on large-scale ASICs for networking, data-center connectivity, or high-bandwidth compute architectures. - Extensive experience in digital ASIC design, micro-architecture development, and RTL implementation using SystemVerilog. - Strong background in high-performance DSP and high-speed datapath design, including pipelined arithmetic units, packet processing engines, memory subsystems, and large-scale control/state machines. - Familiarity with Ethernet protocols and networking standards, including MAC, PCS framing, flow control, and packet-level behaviors. - Proficiency with front-end design flows, including lint, CDC/RDC, synthesis, STA, and power/performance optimization. - Familiarity with advanced process nodes such as 5nm or 3nm and their implications for timing, power, and signal integrity. - BS/MS in Electrical Engineering, Computer Engineering, or related field (PhD is a plus).
Nice to have
- Advanced high-speed DSP algorithm implementation, including adaptive equalization (FFE, DFE, CTLE), channel estimation, and high-throughput filtering architectures. - Experience with FEC architectures such as LDPC, RS, BCH, or other high-speed coding/decoding schemes used in networking and optical interconnects. - Previous PHY design experience, including PMA-level DSP pipelines, equalization blocks, clock recovery, and SerDes-adjacent logic.
Skills: RTL design, SystemVerilog, DSP, high-speed datapaths, Ethernet, AI infrastructure