Principal FPGA Micro-Architect
Originally posted 5 November 2026 by the employer.
About the role
The Principal FPGA Micro-Architect defines and drives the micro-architecture of Lattice's FPGA fabric primitives, optimizing for power, performance, area, and utilization across device families. The role focuses on FPGA architectures targeting Physical AI, Robotics, Space, Data Centers, and edge applications.
What you'll do
- Define the micro-architecture of core fabric primitives, including Programmable Logic Elements, DSP blocks, embedded memory blocks, interconnect routing, configuration memory, carry chains, and clocking structures.
- Drive fabric PPAU (power, performance, area, and utilization) optimization, evaluating implementation and routing feasibility while balancing design trade-offs for modularity and scalability across device generations.
- Develop SystemC/C++ architectural models to conduct performance analysis and evaluate fabric design trade-offs prior to RTL and schematic availability.
- Implement advanced low-power fabric design strategies, including clock and power islands, power gating, dual-rail architectures, and dynamic power mode switching.
- Drive software primitive definition and implementation strategies to ensure fabric elements map efficiently to CAD tools and customer design flows.
- Partner with architecture, DV, firmware, and CAD teams across the full product lifecycle from initial concept through silicon validation and post-silicon debug.
What you'll need
- MS or PhD in Electrical or Computer Engineering with 15+ years of FPGA fabric micro-architecture experience.
- Demonstrated track record of delivering FPGA fabric primitives from architecture definition through tape-out and silicon validation.
- Deep expertise in FPGA fabric elements, including logic elements, DSP blocks, embedded memory blocks, interconnect routing muxes, carry chains, and clocking structures.
- Proficiency in SystemVerilog/Verilog and SystemC/C++ architectural modeling for performance analysis and design trade-off evaluation.
- Extensive experience in advanced low-power design, covering clock and power islands, power gating, multi-rail, and dynamic power mode switching.
- Hands-on experience in silicon validation and post-silicon debug of FPGA fabric blocks, including bring-up, characterization, and root-cause analysis of fabric-level sightings.
More semiconductor jobs: RTL design jobs · San Jose jobs
This role has been open 0 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1086
|
Median days open
61 d
|
Category median salary (all employers)
$188k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Lattice Semiconductor | All employers we track in this specialty (1086 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1086 |
| Open roles in the wider Digital Design & Verification family | 31 | 3495 · 120 employers |
| Median days open | 58 d | 61 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Who's hiring in this category
- Qualcomm · 142 open roles · median 71 d
- Synopsys · 90 open roles · median 48 d
- AMD · 78 open roles · median 47 d
- NXP Semiconductors · 45 open roles · median 104 d
- NVIDIA · 44 open roles · median 61 d
- Analog Devices · 41 open roles · median 51 d
How we counted: 1086 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.