Principal Engineer, SOC Integration - San Jose, California, United States
$219,000 - $351,000 USD yearly
Originally posted 23 July 2026 by the employer.
Focus on prototype and production controller silicon integrating UCIe PHY, DDR controllers, and ARM cores for memory and storage systems.
About the role
As a Principal Engineer, SOC Integration within the DRAM Development Lab (DDL), you will develop prototype and production controllers to enhance memory and storage capability for cloud and data center computing systems. The role focuses on delivering silicon solutions supporting machine learning applications, data analytics, and edge computing.
What you'll do
- Own the integration of SoCs featuring multiple high-speed interfaces. - Review 3rd party IPs including ARM cores, DDR controller, and UCIe PHY. - Integrate third-party IPs with the system bus, peripherals, and CPU cores. - Collaborate with architects and verification engineers to ensure sound design at the SoC level. - Work with physical designers on timing constraints, synthesis, DFT insertion, and static timing analysis.
What you'll need
- BS in Computer/Electrical Engineering or Computer Science with 20+ years of experience, or an MS with 18+ years of experience. - Hands-on knowledge and experience in the ASIC design flow from design to tape out. - Experience with commercial IPs such as UCIe, CPU, Ethernet, and DDR interfaces. - Understanding of performance, power, and area (PPA) trade-offs. - Experience in SoC-level synthesis, timing analysis, lint check, and CDC checks. - Knowledge and experience in AMBA bus fabric, ARM CPU cores, and ARM Co-sight debug features.
Skills: SoC integration, UCIe PHY, AMBA bus fabric, ARM cores, ASIC design flow
This role has been open 88 days — well above the 78-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
472
|
Median days open
78 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (472 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 472 |
| Open roles in the wider Digital Design & Verification family | 14 | 3224 · 116 employers |
| Median days open | 50 d | 78 d (−28 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: SoC integration, UCIe PHY, AMBA bus fabric, ARM cores, ASIC design flow
Who's hiring in this category
- Qualcomm · 73 open roles · median 89 d
- NVIDIA · 56 open roles · median 70 d
- Apple · 36 open roles · median 13 d
- AMD · 34 open roles · median 61 d
- Arm Holdings · 27 open roles · median 116 d
- Micron Technology · 22 open roles · median 108 d
How we counted: 472 open SoC/Chip Architecture (SOC Architecture) roles from 65 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.