Principal Engineer, Signal-Integrity and Power-Integrity - San Jose, CA, United States
$185,000 - $220,000 USD yearly
Originally posted 11 February 2026 by the employer.
About the role
SK hynix America is seeking a Principal Engineer to lead the Signal-Integrity and Power-Integrity (SIPI) strategy for advanced packaging technologies. The role drives the design, analysis, and validation of packaging solutions for HBM and logic-memory integration.
What you'll do
- Define and own the SIPI roadmap for advanced packaging families, aligning technical direction with product and business goals. - Lead the architecture and design of SiP implementations (HBM, interposer, 3D stacks) and validate power delivery and signal integrity from silicon to substrate. - Establish SIPI methodologies covering electromagnetic extraction, multi-port S-parameter modeling, and power-network analysis. - Oversee the end-to-end design flow including package definition, simulation, layout sign-off, and tape-out while improving automation. - Coach senior and junior engineers in SIPI analysis, simulation tool usage, and design verification workflows. - Conduct risk assessments, lead design reviews, and deliver final SIPI sign-off packages meeting performance and reliability requirements.
What you'll need
- Ph.D. in Electrical Engineering or a related field, or a Master's degree with 5+ years of relevant industry experience. - 5+ years of hands-on SIPI engineering experience in advanced semiconductor packaging. - Technical background in 2.5D/3D package architectures, HBM, interposers, TSVs, high-speed I/O standards, and power-delivery networks. - Proficiency with SIPI simulation tools such as Ansys SIwave/RedHawk or Cadence Sigrity. - Direct experience in electromagnetic extraction, multi-port S-parameter analysis, power-network optimization, and tape-out sign-off processes.
Nice to have
- Hands-on experience with 2.5D/3D packaging for HBM, interposers, or GPU-memory integration. - Expertise in power integrity for 3D-stacked memory systems, including PDN impedance profiling and IBIS model validation for HBM. - In-depth familiarity with industry standards such as PCIe Gen5/Gen6, CXL, UCIe, and JEDEC memory specifications. - Familiarity with packaging workflows from ball map definition to tape-out for interposer-based designs. - Proficiency in scripting and automation using Python, TCL, or SKILL. - Experience validating high-speed memory interfaces using oscilloscopes, VNAs, and compliance test platforms for 3D packaging. - Record of published technical papers, patents, or conference presentations in advanced packaging or SIPI.
Skills: sipi, advanced packaging, hbm, interposer, tsps, die-to-die
This role has been open 211 days — well above the 122-day median for Chiplet/Advanced Packaging Design roles.
Chiplet/Advanced Packaging Design · Chiplet Interconnect
|
Open roles in category
38
|
Median days open
122 d
|
Median salary
$219k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SK Hynix America | All employers we track in this specialty (38 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 38 |
| Median days open | 161 d | 122 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $219k |
Skills observed across this category: sipi, advanced packaging, hbm, interposer, tsps, die-to-die
Who's hiring in this category
- Marvell Technology · 5 open roles · median 54 d
- Qualcomm · 5 open roles · median 118 d
- Intel Corporation · 4 open roles · median 42 d
- Micron Technology · 4 open roles · median 165 d
- GlobalFoundries · 3 open roles · median 45 d
- NVIDIA · 3 open roles · median 80 d
How we counted: 38 open Chiplet/Advanced Packaging Design (Chiplet Interconnect) roles from 18 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.