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Ayar Labs

Principal Engineer, Reliability

Ayar Labs San Jose, CA, United States Full-time 5 hours ago
Product Engineering & Quality

$200,000 - $260,000 USD yearly

Join us to architect the reliability roadmap spanning our silicon photonics platform and mixed-signal EICs.

About the role

As Principal Engineer, Reliability, you will be the primary architect of the reliability roadmap for Ayar Labs' silicon photonics platform and mixed-signal EICs. Your expertise will directly influence chiplet co-design, foundry process qualification, and system-level reliability at the PIC-EIC interface.

What you'll do

  • Own the execution and plan for product qualification, including silicon photonics and mixed-signal EIC components, complying with JEDEC, Telcordia (GR-468), and MIL-STD standards.
  • Develop corrective action plans (CAPA) to resolve reliability issues discovered during qualification or in-field deployment.
  • Integrate Design for Reliability (DfR) principles into the earliest stages of the product development lifecycle for both the photonics chiplet and its mixed-signal EIC.
  • Conduct Failure Mode and Effects Analysis (FMEA) across the PIC-EIC system, covering optical elements (waveguides, ring resonators, modulators, photodetectors) and mixed-signal circuit blocks.
  • Serve as the technical lead for reliability with foundry partners across both silicon photonics and CMOS/mixed-signal process nodes.
  • Develop and refine Physics-of-Failure (PoF) models for silicon photonics devices and mixed-signal EIC circuits to predict FIT (Failures in Time) rates and DPPM.

What you'll need

  • Bachelor’s degree in Electrical Engineering, Physics, Materials Science, or a related field.
  • 10+ years of semiconductor reliability experience, with at least 5 years focused specifically on Silicon Photonics and/or Mixed-Signal EIC reliability.
  • Working knowledge of mixed-signal IC design and its reliability mechanisms (electromigration, HCI, NBTI/PBTI, ESD, latch-up) in addition to photonics-specific mechanisms.
  • Deep understanding of foundry process flows and the reliability challenges unique to photonics and CMOS/mixed-signal processes.
  • Proven track record developing aging models (Arrhenius, Coffin-Manson, etc.) for semiconductor and photonic devices.
  • Familiarity with JEDEC, Telcordia (GR-468), and MIL-STD qualification standards.
  • Proficiency in using Python to control lab equipment and DUT.

Nice to have

  • PhD or Master’s degree in Electrical Engineering, Physics, Materials Science, or a related field.
  • Hands-on experience with Python for automated reliability data pipelines.
  • Prior experience co-qualifying an optical chiplet alongside its companion EIC in a co-packaged optics (CPO) architecture.
  • Experience in reliability issues with advanced silicon technologies (7nm, 3nm), advanced packaging (CPO/COWOS) and FAU reliability.
  • Direct external customer interaction experience.

Skills: product qualification, design for reliability, FMEA, physics-of-failure, silicon photonics, mixed-signal EIC

More semiconductor jobs: Reliability engineer jobs · San Jose jobs

Market context

This role has been open 66 days — well above the 44-day median for Reliability Engineering roles.

Reliability Engineering · Reliability Engineering

Open roles in category
518
Median days open
44 d
Category median salary (all employers)
$151k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Ayar Labs compares in Reliability Engineering hiring
Metric Ayar Labs All employers we track in this specialty (518 roles · 78 employers)
Open roles in this specialty 3 518
Open roles in the wider Process, Fab & Equipment family 4 10057 · 117 employers
Median days open 65 d 44 d (+21 d vs this employer)
Median salary (USD postings) — $151k

Skills observed across this category: product qualification, design for reliability, FMEA, physics-of-failure, silicon photonics, mixed-signal EIC

Who's hiring in this category

  • Micron Technology · 75 open roles · median 73 d
  • Infineon Technologies · 42 open roles · median 32 d
  • Renesas Electronics · 26 open roles · median 25 d
  • onsemi · 22 open roles · median 65 d
  • STMicroelectronics · 19 open roles · median 29 d
  • Analog Devices · 16 open roles · median 64 d

How we counted: 518 open Reliability Engineering (Reliability Engineering) roles from 78 employers tracked in the SemiconductorJobs index, counted 8 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.

Ayar Labs

Ayar Labs

Apply now
San Jose, CA, United States
On-site
Full-time
$200,000 - $260,000 USD yearly
5 hours ago

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