Principal Engineer. HBM SIPI - Richardson, TX, United States
Originally posted 15 September 2026 by the employer.
Lead signal and power integrity for High Bandwidth Memory (HBM) solutions that power AI and ML platforms.
About the role
This role is for a Principal Engineer specializing in HBM SIPI, focusing on system-level decisions for HBM development within the Heterogeneous Integration Group. This team builds High Bandwidth Memory solutions that power AI and ML platforms.
What you'll do
- Lead signal integrity channel analysis for 2.5D and 3D silicon interposers, including frequency- and time-domain evaluation.
- Define and drive power delivery architecture, impedance targets, and transient analysis.
- Perform electromagnetic extraction and modeling across PCB, package, and interposer designs.
- Establish SI/PI standards, methodologies, and sign-off criteria for HBM system designs.
- Provide clear technical direction in ambiguous or incomplete design environments.
What you'll need
- 7 years of experience in signal integrity and power integrity modeling and analysis.
- Strong understanding of SI/PI fundamentals, electromagnetics, transmission line theory, and I/O design.
- Hands-on experience with industry-standard SI/PI EDA tools such as ANSYS, Synopsys, Cadence, or Keysight.
Nice to have
- 10+ years of experience in SI and PDN modeling and analysis.
- Experience with 2.5D/3D advanced packaging technologies such as interposer-based designs.
- Background working with high-bandwidth interfaces including HBM, DDR, SERDES, or UCIe.
- Direct ownership of system-level SI/PI sign-off for production silicon.
- Scripting experience with TCL and/or Python to automate SI/PI analysis flows.
Skills: signal integrity, power integrity, HBM, 2.5D and 3D silicon interposers, electromagnetic extraction, SI/PI EDA tools
This role has been open 29 days — well below the 78-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
78 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (241 roles · 47 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 47 | 1412 · 104 employers |
| Median days open | 53 d | 78 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Skills observed across this category: signal integrity, power integrity, HBM, 2.5D and 3D silicon interposers, electromagnetic extraction, SI/PI EDA tools
Who's hiring in this category
- Synopsys · 31 open roles · median 30 d
- AMD · 30 open roles · median 39 d
- Cadence Design Systems · 19 open roles · median 188 d
- Qualcomm · 19 open roles · median 57 d
- Micron Technology (this employer) · 14 open roles · median 53 d
- Apple · 12 open roles · median 16 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 47 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.