Principal Engineer, Electrical Link Architecture

About the role

As a Principal Engineer in Electrical Link Architecture, you own the electrical path end to end, spanning the analog front ends on both sides of the optics, equalization, clocking, and the models used to evaluate links before silicon tapeout. You set block-level electrical specifications for the PHY and AMS teams, partition budgets between the analog front end and DSP, and reconcile silicon validation against architectural models.

What you'll do

• Own the end-to-end electrical architecture and budget of the optical link, spanning drivers, modulators, photodetectors, TIAs, analog front ends, equalization, and clock recovery.
• Partition equalization and gain between the analog front end and DSP, balancing power, area, and link margin through tapeout.
• Translate link requirements into block-level electrical specs (bandwidth, noise, linearity, jitter, offset, swing) and verify blocks close link margin at targeted yield.
• Construct compact models of the analog front end and DSP chain at BER fidelity, alongside Verilog-A models of the electrical/optical interface.
• Lead silicon correlation for the electrical path against validation and SerDes characterization data.
• Run statistical link analysis across corners and Monte Carlo distributions to evaluate link margins and tapeout recommendations.

What you'll need

• BS in Electrical Engineering, Physics, or a related field.
• 8+ years of experience in high-speed wireline or optical link design, spanning analog front ends and link-closing equalization.
• Hands-on design or direct co-design of analog front-end blocks (TIA, CTLE, VGA, sampler, TX driver, clocking) in a high-speed SerDes or optical transceiver.
• Strong command of equalization and clock recovery (CTLE, FFE, DFE, MLSE, ADC-based receivers, adaptation, CDR), including analog versus DSP partitioning.
• Proficiency in Verilog-A and mixed-signal simulation, with working fluency in Cadence Virtuoso, ADE, and Spectre.
• Experience with statistical circuit and link analysis (corners, Monte Carlo, BER, and margin prediction) and Python for scientific computing.

Nice to have

• MS or PhD in Electrical Engineering, Physics, or a related field.
• Experience architecting a SerDes or optical PHY from concept to production silicon, including first-silicon debug.
• Direct experience with optical link electronics, including TIAs, high-swing modulator drivers, microring modulators, thermal control loops, laser RIN, and extinction-ratio budgeting.
• Experience with PAM4 and analog/DSP partitioning at 100 Gb/s per lane and above.
• Familiarity with chiplet/die-to-die interfaces (UCIe), optical transceiver standards (OIF CEI, IEEE 802.3), and shared link-simulation codebases.

Skills: co-packaged optics, optical link, TIA, SerDes, CTLE, Verilog-A

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