Principal Engineer-Design - AZ - Chandler, United States
$75,000 - $232,000 USD yearly
Originally posted 10 March 2026 by the employer.
About the role
Lead the development of digital IP and SoC-level integration for mixed-signal microcontrollers. This hands-on role spans RTL design, integration, and signoff verification with cross-functional collaboration across analog, architecture, validation/test, and product teams.
What you'll do
- Own digital block and subsystem design from concept through tape-out, partnering with architects and system engineers on definition and requirements. - Develop RTL in Verilog / System Verilog for digital peripherals and IP (8/32-bit class blocks), emphasizing robust, reusable design. - Lead block- and SoC-level verification and integration, including simulation regressions, assertions/coverage, UPF / low-power intent, and AMS / mixed-signal verification. - Support Static Timing Analysis (STA), power and IR analysis, and signoff coordination with implementation teams. - Collaborate on Physical Design / APR handoff and signoff, including synthesis handoff, floorplanning awareness, timing/DRC/LVS closure coordination, and ECO support. - Provide technical leadership via design reviews, documentation, debug leadership, and project planning.
What you'll need
- B.S. in Electrical Engineering, Computer Engineering, or related field with 10+ years' experience in ASIC/SoC Digital Design and Verification. - Strong foundations in digital logic / finite state machine design, computer architecture, RTL coding, and SoC integration techniques. - Working knowledge of Physical Design / APR concepts and flows (synthesis, floorplanning, place-and-route, CTS, ECO). - Familiarity with industry EDA flows and tools (Cadence, Synopsys, Siemens), Linux, and Windows. - Scripting skills in Python, Perl, or Tcl for productivity and flow automation.
Nice to have
- M.S. in Electrical Engineering, Computer Engineering, or related field.
Skills: digital IP, SoC-level integration, RTL design, Verilog / System Verilog, Physical Design / APR
This role has been open 185 days — well above the 66-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1081
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (1081 roles · 104 employers) |
|---|---|---|
| Open roles in this specialty | 24 | 1081 |
| Open roles in the wider Digital Design & Verification family | 66 | 3346 · 116 employers |
| Median days open | 78 d | 66 d (+12 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: digital IP, SoC-level integration, RTL design, Verilog / System Verilog, Physical Design / APR
Who's hiring in this category
- Qualcomm · 158 open roles · median 63 d
- Synopsys · 86 open roles · median 40 d
- AMD · 77 open roles · median 45 d
- Analog Devices · 49 open roles · median 56 d
- NXP Semiconductors · 44 open roles · median 100 d
- NVIDIA · 37 open roles · median 52 d
How we counted: 1081 open Digital/RTL Design (RTL Design) roles from 104 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.