Principal Engineer, ASIC Design - San Jose, CA, United States
$145,000 - $298,000 USD yearly
Originally posted 21 July 2026 by the employer.
About the role
This role involves delivering advanced ASIC designs from concept through production silicon, focusing on solid-state drive controllers. You will define micro-architectures, develop RTL, and ensure designs meet performance, timing, and quality goals.
What you'll do
- Design, implement, and debug complex RTL logic and integrate IP into larger subsystems.
- Support front-end design flow including lint, CDC, synthesis, and ECO activities.
- Collaborate with SOC design, verification, STA, and physical design teams to deliver high-quality silicon.
- Develop automation scripts to improve design efficiency and productivity.
- Use AI-assisted tools to enhance debugging, documentation, and code quality.
What you'll need
- MS in Electrical Engineering or equivalent experience with 10+ years of ASIC design experience.
- Strong expertise in Verilog/SystemVerilog for RTL and/or testbench development.
- Deep understanding of digital ASIC design methodologies and full design flow.
- Experience with industry-standard tools such as Design Compiler, PrimeTime, or similar.
- Proven experience working on large-scale complex design projects.
Nice to have
- Experience with AMBA AXI/AHB interconnect protocols.
- Familiarity with storage or memory protocols such as NVMe, SCSI, CXL, or DDR.
- Experience with verification and CAD tools such as ncsim or Formality.
- Proficiency in Python or other programming languages for design automation.
- Familiarity with AI/ML concepts and applying AI-enabled features in EDA tools for productivity improvements.
Skills: NAND, analog/mixed signal circuit design, page buffers, block selectors, HSPICE
This role has been open 194 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: NAND, analog/mixed signal circuit design, page buffers, block selectors, HSPICE
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.