Principal Emulation Engineer - San Jose, California, United States
$207,000 - $230,000 USD yearly
Originally posted 9 September 2026 by the employer — open 0 days.
About the role
As a Principal Emulation Engineer, you will build and operate emulation environments that let verification teams stress-test complex ASICs before silicon. You'll help validate the switching, PCIe, Ethernet, memory, and storage interfaces that connect the compute fabric.
What you'll do
- Architect, build, and maintain emulation environments for complex ASICs and SoCs.
- Integrate RTL, transactors, protocol models, software, and test infrastructure for hardware-software co-simulation.
- Enable verification teams to stress-test designs with scalable, repeatable emulation workflows.
- Verify hardware-software interfaces and system behaviors in partnership with logic designers, firmware engineers, and verification teams.
- Exercise and debug PCI Express Gen 3 and above, Ethernet, DDR, NVMe, SPI, I2C/I3C, and similar interfaces.
What you'll need
- 10+ years of experience in hardware emulation, ASIC/SoC verification, or a related field.
- Experience architecting and deploying emulation environments (e.g., Palladium, ZeBu, Veloce).
- Hands-on experience with hardware-software co-simulation and bring-up of ASICs.
- Strong knowledge of SystemVerilog, C, and scripting languages (e.g., Python, Perl).
- Deep understanding of high-speed protocols such as PCI Express, Ethernet, DDR, NVMe, SPI, or I2C/I3C.
- Expertise in debug methodologies across the emulation stack, including RTL, transactors, and software.
Skills: emulation environments, stress-test ASICs, hardware-software co-simulation, PCI Express, SystemVerilog
This role has been open 0 days — well below the 56-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1123
|
Median days open
56 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1123 roles · 90 employers) |
|---|---|---|
| Open roles in category | 13 | 1123 |
| Median days open | 77 d | 56 d (+21 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: emulation environments, stress-test ASICs, hardware-software co-simulation, PCI Express, SystemVerilog
Who's hiring in this category
- Qualcomm · 98 open roles · median 48 d
- AMD · 97 open roles · median 29 d
- NVIDIA · 95 open roles · median 58 d
- Micron Technology · 53 open roles · median 96 d
- Arm Holdings · 49 open roles · median 65 d
- Marvell Technology · 48 open roles · median 115 d
How we counted: 1123 open Design Verification (Design Verification) roles from 90 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Figures refresh nightly.