Principal Digital Verification Engineer
Originally posted 17 September 2026 by the employer.
Work on memory interface IP solutions.
About the role
This role involves building comprehensive verification environments for complex digital designs, focusing on memory PHYs. You will work within the IP Group, specializing in interface IP solutions for memory interfaces.
What you'll do
- Develop comprehensive testplans and functional coverage models for training firmware running on RTL models of memory PHYs.
- Build and maintain testbench infrastructure in SystemVerilog and UVM.
- Create test cases that cover success paths, corner cases, and negative scenarios based on standard specifications and feature enhancements.
- Debug complex issues across firmware, RTL, and testbench layers using simulation and waveform analysis tools.
- Participate in technical reviews with architecture and implementation teams to influence design decisions.
- Mentor junior engineers on testbench design, debugging techniques, and verification methodology, and collaborate on verification strategy.
What you'll need
- BSc in Electrical Engineering, Computer Engineering, or related field with 12+ years of verification experience; MSc with 10+ years; or PhD with 8+ years.
- Deep proficiency in SystemVerilog and UVM, with a track record of building reusable testbench components and verification environments.
- Strong command of simulation tools, waveform debuggers, and the ability to trace issues across multiple abstraction layers.
- Solid understanding of C and experience with software/hardware co-simulation.
- Experience with assertion-based verification, coverage analysis, and protocol-oriented performance debug.
- Comfort working in Linux environments with scripting for regression systems, build automation, and source control workflows.
Skills: SystemVerilog, UVM, testplans, functional coverage, memory PHYs
This role has been open 38 days — well below the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Synopsys | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 72 | 1268 |
| Open roles in the wider Digital Design & Verification family | 180 | 3328 · 116 employers |
| Median days open | 42 d | 67 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog, UVM, testplans, functional coverage, memory PHYs
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys (this employer) · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.