Principal Digital IC Design Engineer - Richardson, TX, United States
Originally posted 2 October 2026 by the employer.
About the role
This role involves leading the full-flow ASIC development lifecycle from architectural concepts and RTL design to physical sign-off and silicon bring-up.
What you'll do
- Define, establish, and optimize ASIC design methodologies and full-flow architectures.
- Act as the technical authority to align Architecture, RTL Design, Verification, and Physical Design domains.
- Provide expert guidance on complex engineering trade-offs evaluating Power, Performance, and Area (PPA).
- Translate system-level product requirements into SoC/ASIC microarchitectures.
- Write high-quality, scalable, and synthesizable hardware description code using SystemVerilog/Verilog.
- Drive full chip-level and block-level execution through synthesis, floorplanning, and automated Place & Route (P&R) flows.
- Formulate and sign off on rigorous Timing Constraints and execute Static Timing Analysis (STA).
- Oversee structural physical verification including DRC, LVS, and ERC checks.
What you'll need
- Bachelor’s degree in Electrical Engineering.
- 12+ years of industry experience in digital ASIC design and implementation with multiple successful commercial tape-outs.
- Mastery of SystemVerilog and Verilog.
- Comprehensive hands-on command of the RTL-to-GDSII flow (Logic Synthesis, Floorplanning, CTS, P&R, STA, and Physical Verification).
- Deep proficiency with flagship EDA toolsuites from Synopsys (Design Compiler, IC Compiler II, PrimeTime) or Cadence (Genus, Innovus, Tempus).
- Strong programming proficiency in Python, TCL, and Bash/Perl for methodology customization and CAD data manipulation.
- Direct experience with silicon bring-up, hardware debugging, and lab evaluation.
Nice to have
- Master’s or PhD degree in Electrical Engineering.
- Prior experience with Power Management IC’s.
Skills: ASIC design, SystemVerilog, RTL-to-GDSII, STA, Physical Verification, EDA tools
This role has been open 0 days — well below the 59-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
984
|
Median days open
59 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | QORVO | All employers we track in this specialty (984 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 984 |
| Open roles in the wider Digital Design & Verification family | 3 | 3119 · 115 employers |
| Median days open | 4 d | 59 d (−55 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: ASIC design, SystemVerilog, RTL-to-GDSII, STA, Physical Verification, EDA tools
Who's hiring in this category
- Qualcomm · 148 open roles · median 56 d
- Synopsys · 68 open roles · median 22 d
- AMD · 65 open roles · median 44 d
- NXP Semiconductors · 50 open roles · median 70 d
- Analog Devices · 45 open roles · median 37 d
- NVIDIA · 45 open roles · median 56 d
How we counted: 984 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 2 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.