Principal Digital Engineer (DFT Design) - Chandler, United States
Verification, Validation & Test
Originally posted 12 August 2026 by the employer.
About the role
This role involves designing complex chips, including analog and digital control circuitry, with a focus on digital DFT design for automotive PMIC products.
What you'll do
- Insert DFT/Scan on digital logic, perform ATPG, and validate test patterns on pre and post layout gate level netlist.
- Deliver test patterns to the test engineering team and validate them on silicon.
- Insert Logicbist with industry standard tools.
- Participate in digital design flow aspects such as Micro-architecture, Design partitioning, RTL Verilog / System Verilog coding, DFT insertion, and generating Timing Constraints.
- Debug scan pattern failures on ATE and fix scan patterns.
- Write detailed design documents, DFT specifications, and review specifications with stakeholders.
What you'll need
- 12+ years of experience with a Master's or 15+ years with a Bachelor's in digital design and DFT implementation.
- Hands-on experience in Scan insertion, improving scan coverage, ATPG, and Logicbist insertion during synthesis or RTL.
- Experience with gate level simulations using test patterns and delivering validated patterns to the Test engineering team.
- Basic digital RTL coding experience and synthesis exposure.
- Experience with at least 8 tapeouts with hands-on DFT/Scan experience.
- Solid understanding of synthesizable design, timing constraints, and exceptions.
- Experience with industry standard Synopsys, Cadence, Mentor, Siemens tools for scan, Logicbist insertion, and ATPG.
Nice to have
- Mixed signal experience.
- Exposure to automotive test requirements and ASIL.
- Tetramax experience.
Market context
This role has been open 66 days — slightly above the 57-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
242
|
Median days open
57 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (242 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 242 |
| Open roles in the wider Digital Design & Verification family | 86 | 3202 · 115 employers |
| Median days open | 60 d | 57 d (+3 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Who's hiring in this category
- AMD · 39 open roles · median 43 d
- NVIDIA · 23 open roles · median 35 d
- Qualcomm · 23 open roles · median 100 d
- NXP Semiconductors · 18 open roles · median 65 d
- Synopsys · 14 open roles · median 24 d
- Micron Technology · 10 open roles · median 64 d
How we counted: 242 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.